Ahmed Bougacha 3c9fb6e1ad [AArch64] Improve codegen of store lane instructions by avoiding GPR usage. ... We used to generate code similar to: umov.b w8, v0[2] strb w8, [x0, x1] because the STR*ro* patterns were preferred to ST1*. Instead, we can avoid going through GPRs, and generate: add x8, x0, x1 st1.b { v0 }[2], [x8] This patch increases the ST1* AddedComplexity to achieve that. rdar://16372710 Differential Revision: http://reviews.llvm.org/D6202 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225183 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-05 17:10:26 +00:00
..
AsmParser	Minor cleanup to all the switches after MatchInstructionImpl in all the AsmParsers.	2015-01-03 08:16:34 +00:00
Disassembler
InstPrinter
MCTargetDesc	Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert.	2015-01-05 10:15:49 +00:00
TargetInfo
Utils
AArch64.h
AArch64.td
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AddressTypePromotion.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp
AArch64BranchRelaxation.cpp
AArch64CallingConvention.h
AArch64CallingConvention.td
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandPseudoInsts.cpp
AArch64FastISel.cpp
AArch64FrameLowering.cpp	ARM/AArch64: Attach the FrameSetup MIFlag to CFI instructions.	2014-12-16 00:20:49 +00:00
AArch64FrameLowering.h
AArch64InstrAtomics.td
AArch64InstrFormats.td
AArch64InstrInfo.cpp
AArch64InstrInfo.h
AArch64InstrInfo.td	[AArch64] Improve codegen of store lane instructions by avoiding GPR usage.	2015-01-05 17:10:26 +00:00
AArch64ISelDAGToDAG.cpp
AArch64ISelLowering.cpp	ARM: permit tail calls to weak externals on COFF	2015-01-03 21:35:00 +00:00
AArch64ISelLowering.h
AArch64LoadStoreOptimizer.cpp
AArch64MachineCombinerPattern.h
AArch64MachineFunctionInfo.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RegisterInfo.cpp
AArch64RegisterInfo.h
AArch64RegisterInfo.td
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp
AArch64Subtarget.h
AArch64TargetMachine.cpp	Enable MachineVerifier in debug mode for X86, ARM, AArch64, Mips.	2014-12-11 23:18:03 +00:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp
CMakeLists.txt
LLVMBuild.txt
Makefile