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https://github.com/c64scene-ar/llvm-6502.git
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5d6365c80c
This is mostly achieved by providing the correct register class manually, because getRegClassFor always returns the GPR*AllRegClass for MVT::i32 and MVT::i64. Also cleanup the code to use the FastEmitInst_* method whenever possible. This makes sure that the operands' register class is properly constrained. For all the remaining cases this adds the missing constrainOperandRegClass calls for each operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216225 91177308-0d34-0410-b5e6-96231b3b80d8
31 lines
705 B
LLVM
31 lines
705 B
LLVM
; RUN: llc -mtriple=aarch64-unknown-unknown -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=aarch64-unknown-unknown -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
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define void @store_i8(i8* %a) {
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; CHECK-LABEL: store_i8
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; CHECK: strb wzr, [x0]
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store i8 0, i8* %a
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ret void
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}
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define void @store_i16(i16* %a) {
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; CHECK-LABEL: store_i16
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; CHECK: strh wzr, [x0]
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store i16 0, i16* %a
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ret void
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}
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define void @store_i32(i32* %a) {
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; CHECK-LABEL: store_i32
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; CHECK: str wzr, [x0]
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store i32 0, i32* %a
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ret void
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}
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define void @store_i64(i64* %a) {
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; CHECK-LABEL: store_i64
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; CHECK: str xzr, [x0]
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store i64 0, i64* %a
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ret void
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}
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