Ulrich Weigand cb1b3ad4e1 [SystemZ] Support RISBGN instruction on zEC12 ... So far, we do not yet support any instruction specific to zEC12. Most of the facilities added with zEC12 are indeed not very useful to compiler code generation, but there is one exception: the miscellaneous-extensions facility provides the RISBGN instruction, which is a variant of RISBG that does not set the condition code. Add support for this facility, MC support for RISBGN, and CodeGen support for prefering RISBGN over RISBG on zEC12, unless we can actually make use of the condition code set by RISBG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233690 91177308-0d34-0410-b5e6-96231b3b80d8		2015-03-31 12:58:17 +00:00
..
AArch64	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
ARM	[ARM] Fix some non-portable shell syntax in r233301's tests	2015-03-26 19:24:13 +00:00
AsmParser	Add support for .ifnes psuedo-op.	2015-03-18 14:20:54 +00:00
COFF	[opaque pointer type] Add textual IR support for explicit type parameter to gep operator	2015-03-13 18:20:45 +00:00
Disassembler	[SystemZ] Support RISBGN instruction on zEC12	2015-03-31 12:58:17 +00:00
ELF	MC: For variable symbols, maintain MCSymbol::Section as a cache.	2015-03-30 20:41:21 +00:00
Hexagon
MachO	MC: For variable symbols, maintain MCSymbol::Section as a cache.	2015-03-30 20:41:21 +00:00
Markup
Mips	[mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction.	2015-03-17 13:17:44 +00:00
PowerPC	[PowerPC] Add asm parser support for bitmask forms of rotate-and-mask instructions	2015-03-28 19:42:41 +00:00
R600
Sparc
SystemZ	[SystemZ] Support RISBGN instruction on zEC12	2015-03-31 12:58:17 +00:00
X86	Fix the operand encoding in the test instruction.	2015-03-31 12:31:55 +00:00