Vasileios Kalintiris 7db2065236 [mips] Enable code generation for MIPS-III. ... Summary: This commit enables the MIPS-III target and adds support for code generation of SELECT nodes. We have to use pseudo-instructions with custom inserters for these nodes as MIPS-III CPUs do not have conditional-move instructions. Depends on D6212 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6464 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224128 91177308-0d34-0410-b5e6-96231b3b80d8		2014-12-12 15:16:46 +00:00
..
call.ll	[mips][mips64r6] Use JALR for indirect branches instead of JR (which is not available on MIPS32r6/MIPS64r6)	2014-07-09 10:21:59 +00:00
indirectbr.ll	[mips][mips64r6] Use JALR for indirect branches instead of JR (which is not available on MIPS32r6/MIPS64r6)	2014-07-09 10:21:59 +00:00
mul.ll	[mips] Add preliminary support for the MIPS II target.	2014-11-11 11:43:55 +00:00
ret.ll
select.ll	[mips] Enable code generation for MIPS-III.	2014-12-12 15:16:46 +00:00