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19a99df130
The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194755 91177308-0d34-0410-b5e6-96231b3b80d8
57 lines
1.7 KiB
C++
57 lines
1.7 KiB
C++
//===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for R600RegisterInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef R600REGISTERINFO_H_
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#define R600REGISTERINFO_H_
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#include "AMDGPURegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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namespace llvm {
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class R600TargetMachine;
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struct R600RegisterInfo : public AMDGPURegisterInfo {
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AMDGPUTargetMachine &TM;
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RegClassWeight RCW;
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R600RegisterInfo(AMDGPUTargetMachine &tm);
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virtual BitVector getReservedRegs(const MachineFunction &MF) const;
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/// \param RC is an AMDIL reg class.
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///
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/// \returns the R600 reg class that is equivalent to \p RC.
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virtual const TargetRegisterClass *getISARegClass(
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const TargetRegisterClass *RC) const;
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/// \brief get the HW encoding for a register's channel.
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unsigned getHWRegChan(unsigned reg) const;
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virtual unsigned getHWRegIndex(unsigned Reg) const;
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/// \brief get the register class of the specified type to use in the
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/// CFGStructurizer
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virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
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virtual const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const;
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// \returns true if \p Reg can be defined in one ALU caluse and used in another.
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virtual bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
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};
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} // End namespace llvm
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#endif // AMDIDSAREGISTERINFO_H_
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