llvm-6502/lib/CodeGen/SelectionDAG
Chris Lattner cc2210b4fa Only transform (sext (truncate x)) -> (sextinreg x) if before legalize or
if the target supports the resultant sextinreg


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24632 91177308-0d34-0410-b5e6-96231b3b80d8
2005-12-07 18:02:05 +00:00
..
DAGCombiner.cpp Only transform (sext (truncate x)) -> (sextinreg x) if before legalize or 2005-12-07 18:02:05 +00:00
LegalizeDAG.cpp Teach the SelectionDAG ISel how to turn ConstantPacked values into 2005-12-06 06:18:55 +00:00
Makefile
ScheduleDAG.cpp Support multiple ValueTypes per RegisterClass, needed for upcoming vector 2005-12-01 04:51:06 +00:00
SelectionDAG.cpp Teach the SelectionDAG ISel how to turn ConstantPacked values into 2005-12-06 06:18:55 +00:00
SelectionDAGISel.cpp Teach the SelectionDAG ISel how to turn ConstantPacked values into 2005-12-06 06:18:55 +00:00
SelectionDAGPrinter.cpp Added an index field to GlobalAddressSDNode so it can represent X+12, etc. 2005-11-30 02:04:11 +00:00
TargetLowering.cpp Add the majority of the vector machien value types we expect to support, 2005-11-29 05:45:29 +00:00