mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
110 lines
3.4 KiB
LLVM
110 lines
3.4 KiB
LLVM
; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
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; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
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; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6
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; RUN: llc < %s -march=mipsel -mcpu=mips4 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
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; RUN: llc < %s -march=mipsel -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
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; RUN: llc < %s -march=mipsel -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV
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; RUN: llc < %s -march=mipsel -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64R6
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@g1 = external global i32
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define i32 @sel_icmp_nez_i32_z0(i32 signext %s) nounwind readonly {
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entry:
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; ALL-LABEL: sel_icmp_nez_i32_z0:
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; 32-CMOV: lw $2, 0(${{[0-9]+}})
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; 32-CMOV: movn $2, $zero, $4
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; 32R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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; 32R6: seleqz $2, $[[R0]], $4
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; 64-CMOV: lw $2, 0(${{[0-9]+}})
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; 64-CMOV: movn $2, $zero, $4
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; 64R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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; 64R6: seleqz $2, $[[R0]], $4
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%tobool = icmp ne i32 %s, 0
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%0 = load i32, i32* @g1, align 4
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%cond = select i1 %tobool, i32 0, i32 %0
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ret i32 %cond
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}
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define i32 @sel_icmp_nez_i32_z1(i32 signext %s) nounwind readonly {
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entry:
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; ALL-LABEL: sel_icmp_nez_i32_z1:
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; 32-CMOV: lw $2, 0(${{[0-9]+}})
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; 32-CMOV: movz $2, $zero, $4
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; 32R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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; 32R6: selnez $2, $[[R0]], $4
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; 64-CMOV: lw $2, 0(${{[0-9]+}})
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; 64-CMOV: movz $2, $zero, $4
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; 64R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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; 64R6: selnez $2, $[[R0]], $4
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%tobool = icmp ne i32 %s, 0
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%0 = load i32, i32* @g1, align 4
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%cond = select i1 %tobool, i32 %0, i32 0
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ret i32 %cond
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}
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@g2 = external global i64
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define i64 @sel_icmp_nez_i64_z0(i64 %s) nounwind readonly {
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entry:
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; ALL-LABEL: sel_icmp_nez_i64_z0:
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; 32-CMOV-DAG: lw $[[R0:2]], 0(${{[0-9]+}})
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; 32-CMOV-DAG: lw $[[R1:3]], 4(${{[0-9]+}})
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; 32-CMOV-DAG: movn $[[R0]], $zero, $4
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; 32-CMOV-DAG: movn $[[R1]], $zero, $4
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; 32R6-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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; 32R6-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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; 32R6-DAG: or $[[CC:[0-9]+]], $4, $5
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; 32R6-DAG: seleqz $2, $[[R0]], $[[CC]]
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; 32R6-DAG: seleqz $3, $[[R1]], $[[CC]]
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; 64-CMOV: ld $2, 0(${{[0-9]+}})
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; 64-CMOV: movn $2, $zero, $4
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; 64R6: ld $[[R0:[0-9]+]], 0(${{[0-9]+}})
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; 64R6: seleqz $2, $[[R0]], $4
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%tobool = icmp ne i64 %s, 0
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%0 = load i64, i64* @g2, align 4
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%cond = select i1 %tobool, i64 0, i64 %0
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ret i64 %cond
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}
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define i64 @sel_icmp_nez_i64_z1(i64 %s) nounwind readonly {
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entry:
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; ALL-LABEL: sel_icmp_nez_i64_z1:
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; 32-CMOV-DAG: lw $[[R0:2]], 0(${{[0-9]+}})
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; 32-CMOV-DAG: lw $[[R1:3]], 4(${{[0-9]+}})
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; 32-CMOV-DAG: movz $[[R0]], $zero, $4
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; 32-CMOV-DAG: movz $[[R1]], $zero, $4
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; 32R6-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}})
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; 32R6-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}})
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; 32R6-DAG: or $[[CC:[0-9]+]], $4, $5
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; 32R6-DAG: selnez $2, $[[R0]], $[[CC]]
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; 32R6-DAG: selnez $3, $[[R1]], $[[CC]]
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; 64-CMOV: ld $2, 0(${{[0-9]+}})
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; 64-CMOV: movz $2, $zero, $4
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; 64R6: ld $[[R0:[0-9]+]], 0(${{[0-9]+}})
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; 64R6: selnez $2, $[[R0]], $4
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%tobool = icmp ne i64 %s, 0
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%0 = load i64, i64* @g2, align 4
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%cond = select i1 %tobool, i64 %0, i64 0
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ret i64 %cond
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}
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