Tilmann Scheller cca1146119 ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands. ... As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints: LDRD<c> <Rt>, <Rt2>, ... (a) Rt must be even-numbered and not r14 (b) Rt2 must be R(t+1) If those two constraints are not met the result of executing the instruction will be unpredictable. Constraint (b) was already enforced, this commit adds support for constraint (a). Fixes rdar://14479793. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191520 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-27 13:28:17 +00:00
..
Analysis
AsmParser
Bitcode
CodeGen
DebugInfo
ExecutionEngine
IR
IRReader
Linker
LTO
MC
Object
Option
Support
TableGen
Target	ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.	2013-09-27 13:28:17 +00:00
Transforms
CMakeLists.txt
LLVMBuild.txt
Makefile