.. |
.cvsignore
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ignore generated files
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2005-09-07 23:47:44 +00:00 |
Alpha.h
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ret 0; works, not much else
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2005-10-20 00:28:31 +00:00 |
Alpha.td
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Alpha Scheduling classes
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2006-03-09 17:16:45 +00:00 |
AlphaAsmPrinter.cpp
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Add support for 'special' llvm globals like debug info and static ctors/dtors.
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2006-03-09 06:14:35 +00:00 |
AlphaCodeEmitter.cpp
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Add explicit #includes of <iostream>
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2006-01-22 23:41:00 +00:00 |
AlphaInstrFormats.td
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Alpha Scheduling classes
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2006-03-09 17:16:45 +00:00 |
AlphaInstrInfo.cpp
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these are copies too
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2006-03-09 18:18:51 +00:00 |
AlphaInstrInfo.h
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isStoreToStackSlot
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2006-02-03 03:07:37 +00:00 |
AlphaInstrInfo.td
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fcopysign for mixed mode
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2006-03-09 17:56:33 +00:00 |
AlphaISelDAGToDAG.cpp
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#include Intrinsics.h into all dag isels
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2006-03-25 06:47:10 +00:00 |
AlphaISelLowering.cpp
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This makes McCat/12-IOtest go 8x faster or so
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2006-04-02 21:08:39 +00:00 |
AlphaISelLowering.h
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Alpha Scheduling classes
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2006-03-09 17:16:45 +00:00 |
AlphaJITInfo.cpp
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Remove a 'using namespace std'.
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2006-01-01 22:20:31 +00:00 |
AlphaJITInfo.h
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Alpha JIT (beta)
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2005-07-22 20:52:16 +00:00 |
AlphaRegisterInfo.cpp
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Expose base register for DwarfWriter. Refactor code accordingly.
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2006-03-28 13:48:33 +00:00 |
AlphaRegisterInfo.h
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Expose base register for DwarfWriter. Refactor code accordingly.
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2006-03-28 13:48:33 +00:00 |
AlphaRegisterInfo.td
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Add dwarf register numbering to register data.
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2006-03-24 21:15:58 +00:00 |
AlphaRelocations.h
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support bsr, and more .td simplification
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2005-07-28 18:14:47 +00:00 |
AlphaSchedule.td
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Alpha Scheduling classes
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2006-03-09 17:16:45 +00:00 |
AlphaSubtarget.cpp
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Give full control of subtarget features over to table generated code.
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2005-10-26 17:30:34 +00:00 |
AlphaSubtarget.h
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Alpha Scheduling classes
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2006-03-09 17:16:45 +00:00 |
AlphaTargetMachine.cpp
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Eliminate IntrinsicLowering from TargetMachine.
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2006-03-23 05:43:16 +00:00 |
AlphaTargetMachine.h
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Eliminate IntrinsicLowering from TargetMachine.
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2006-03-23 05:43:16 +00:00 |
Makefile
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Autogen subtarget information from .td files.
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2005-10-23 22:15:34 +00:00 |