llvm-6502/test/CodeGen
Sanjay Patel 956d6f0cf5 Model sqrtsd as a binary operation with one source operand tied to the destination (PR14221)
This patch fixes the following miscompile:

define void @sqrtsd(<2 x double> %a) nounwind uwtable ssp {
  %0 = tail call <2 x double> @llvm.x86.sse2.sqrt.sd(<2 x double> %a) nounwind 
  %a0 = extractelement <2 x double> %0, i32 0
  %conv = fptrunc double %a0 to float
  %a1 = extractelement <2 x double> %0, i32 1
  %conv3 = fptrunc double %a1 to float
  tail call void @callee2(float %conv, float %conv3) nounwind
  ret void
}

Current codegen:

sqrtsd	%xmm0, %xmm1        ## high element of %xmm1 is undef here
xorps	%xmm0, %xmm0
cvtsd2ss	%xmm1, %xmm0
shufpd	$1, %xmm1, %xmm1
cvtsd2ss	%xmm1, %xmm1 ## operating on undef value
jmp	_callee

This is a continuation of http://llvm.org/viewvc/llvm-project?view=revision&revision=224624 ( http://reviews.llvm.org/D6330 ) 
which was itself a continuation of r167064 ( http://llvm.org/viewvc/llvm-project?view=revision&revision=167064 ).

All of these patches are partial fixes for PR14221 ( http://llvm.org/bugs/show_bug.cgi?id=14221 ); 
this should be the final patch needed to resolve that bug.

Differential Revision: http://reviews.llvm.org/D6885



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227111 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-26 18:42:16 +00:00
..
AArch64 [AArch64][LoadStoreOptimizer] Form LDPSW when possible. 2015-01-24 01:25:54 +00:00
ARM This patch fixes issue with lowering below mentioned pattern :- 2015-01-23 09:10:03 +00:00
BPF bpf: add missing lit.local.cfg 2015-01-24 18:20:52 +00:00
CPP
Generic getMangledTypeStr: clarify how it mangles types, and add tests 2015-01-14 23:05:17 +00:00
Hexagon [Hexagon] Converting multiply and accumulate with immediate intrinsics to patterns. 2015-01-21 18:13:15 +00:00
Inputs IR: Move MDLocation into place 2015-01-14 22:27:36 +00:00
Mips Move the Mips target to storing the ABI in the TargetMachine rather 2015-01-26 17:33:46 +00:00
MSP430
NVPTX Check that the TLI callback enableAggressiveFMAFusion has the desired effect on FMA folding. 2015-01-14 15:36:28 +00:00
PowerPC [PowerPC] Revert ppc64le-aggregates.ll test changes from r227053 2015-01-25 18:18:54 +00:00
R600 R600/SI: Emit .hsa.version section for amdhsa OS 2015-01-23 23:59:08 +00:00
SPARC Use the integrated assembler by default on SPARC. 2015-01-14 07:53:39 +00:00
SystemZ Use the integrated assembler as default on SystemZ 2015-01-13 19:45:16 +00:00
Thumb IR: Move MDLocation into place 2015-01-14 22:27:36 +00:00
Thumb2
X86 Model sqrtsd as a binary operation with one source operand tied to the destination (PR14221) 2015-01-26 18:42:16 +00:00
XCore IR: Move MDLocation into place 2015-01-14 22:27:36 +00:00