Juergen Ributzka ccf53013cd [FastISel][AArch64] Fix simplify address when the address comes from a shift. ... When the address comes directly from a shift instruction then the address computation cannot be folded into the memory instruction, because the zero register is not available as a base register. Simplify addess needs to emit the shift instruction and use the result as base register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216621 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-27 21:38:33 +00:00
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AArch64	[FastISel][AArch64] Fix simplify address when the address comes from a shift.	2014-08-27 21:38:33 +00:00
ARM	ARM: Add patterns for dbg	2014-08-26 12:47:26 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Don't use odd-numbered float registers for double arguments for fastcc	2014-08-22 09:23:22 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add support for dcbtst and icbt (prefetch)	2014-08-23 23:21:04 +00:00
R600	R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignment	2014-08-22 18:49:35 +00:00
SPARC
SystemZ
Thumb	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
Thumb2	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
X86	[x86] Fix a regression introduced with r213897 for 32-bit targets where	2014-08-27 11:39:47 +00:00
XCore