Saleem Abdulrasool cde1f2eae2 ARM: enable tail call optimisation on Thumb 2 ... Tail call optimisation was previously disabled on all targets other than iOS5.0+. This enables the tail call optimisation on all Thumb 2 capable platforms. The test adjustments are to remove the IR hint "tail" to function invocation. The tests were designed assuming that tail call optimisations would not kick in which no longer holds true. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203575 91177308-0d34-0410-b5e6-96231b3b80d8		2014-03-11 15:09:44 +00:00
..
AArch64	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
ARM	ARM: enable tail call optimisation on Thumb 2	2014-03-11 15:09:44 +00:00
CPP
Generic	CommandLine: Exit successfully for -version and -help	2014-02-28 19:08:01 +00:00
Hexagon	Fix broken CHECK lines	2014-02-16 07:31:05 +00:00
Inputs
Mips	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
MSP430
NVPTX	Followup to r203483 - add test.	2014-03-10 20:36:04 +00:00
PowerPC	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
R600	R600/SI: Using SGPRs is illegal for instructions that read carry-out from VCC	2014-03-07 20:12:39 +00:00
SPARC	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
SystemZ	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
Thumb	Add triples to try to fix the windows bots.	2014-02-13 16:49:47 +00:00
Thumb2	ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) wouldn't affect CPSR in an IT block	2014-02-26 11:27:28 +00:00
X86	IR: add a second ordering operand to cmpxhg for failure	2014-03-11 10:48:52 +00:00
XCore	[XCore] Add support for the "m" inline asm constraint.	2014-03-06 16:37:48 +00:00