Jim Grosbach ced674e470 ARM: Use a dedicated intrinsic for vector bitwise select. ... The expression based expansion too often results in IR level optimizations splitting the intermediate values into separate basic blocks, preventing the formation of the VBSL instruction as the code author intended. In particular, LICM would often hoist part of the computation out of a loop. rdar://11011471 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164340 91177308-0d34-0410-b5e6-96231b3b80d8		2012-09-21 00:18:20 +00:00
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ARM	ARM: Use a dedicated intrinsic for vector bitwise select.	2012-09-21 00:18:20 +00:00
CellSPU	Add test triples to fix win32 failures. Revert workaround from r161292.	2012-08-08 20:31:37 +00:00
CPP	test commit	2012-07-18 17:53:05 +00:00
Generic	BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle	2012-08-24 18:14:27 +00:00
Hexagon	LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the	2012-09-05 16:01:40 +00:00
MBlaze
Mips	Handled unaligned load/stores properly in Mips16	2012-09-15 01:02:03 +00:00
MSP430	Reapply r161633-161634 "Partition use lists so defs always come before uses.""	2012-08-10 00:21:30 +00:00
NVPTX
PowerPC	Specify cpu to get the correct instruction ordering. Remove XFAIL.	2012-09-20 14:59:42 +00:00
SPARC	Move load_to_switch.ll to test/CodeGen/SPARC/	2012-09-19 09:25:03 +00:00
Thumb	Fix Thumb2 fixup kind in the integrated-as.	2012-09-01 15:06:36 +00:00
Thumb2	Use vld1 / vst2 for unaligned v2f64 load / store. e.g. Use vld1.16 for 2-byte	2012-09-18 01:42:45 +00:00
X86	Fix broken check lines.	2012-09-20 19:54:13 +00:00
XCore