Sanjay Patel cf9661c6f9 Fix a logic bug in x86 vector codegen: sext (zext (x) ) != sext (x) (PR20472). ... Remove a block of code from LowerSIGN_EXTEND_INREG() that was added with: http://llvm.org/viewvc/llvm-project?view=revision&revision=177421 And caused: http://llvm.org/bugs/show_bug.cgi?id=20472 (more analysis here) http://llvm.org/bugs/show_bug.cgi?id=18054 The testcases confirm that we (1) don't remove a zext op that is necessary and (2) generate a pmovz instead of punpck if SSE4.1 is available. Although pmovz is 1 byte longer, it allows folding of the load, and so saves 3 bytes overall. Differential Revision: http://reviews.llvm.org/D4909 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216679 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-28 18:59:22 +00:00
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AArch64	Generate CMN when comparing a short int with minus	2014-08-28 04:59:53 +00:00
ARM	ARM: Add patterns for dbg	2014-08-26 12:47:26 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Don't use odd-numbered float registers for double arguments for fastcc	2014-08-22 09:23:22 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add support for dcbtst and icbt (prefetch)	2014-08-23 23:21:04 +00:00
R600	R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignment	2014-08-22 18:49:35 +00:00
SPARC
SystemZ
Thumb	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
Thumb2	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
X86	Fix a logic bug in x86 vector codegen: sext (zext (x) ) != sext (x) (PR20472).	2014-08-28 18:59:22 +00:00
XCore