mirror of
https://github.com/c64scene-ar/llvm-6502.git
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49683f3c96
The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
147 lines
3.2 KiB
LLVM
147 lines
3.2 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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define i16 @cvt_i16_f32(float %x) {
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; CHECK: cvt.rzi.u16.f32 %rs{{[0-9]+}}, %f{{[0-9]+}};
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; CHECK: ret;
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%a = fptoui float %x to i16
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ret i16 %a
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}
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define i16 @cvt_i16_f64(double %x) {
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; CHECK: cvt.rzi.u16.f64 %rs{{[0-9]+}}, %fl{{[0-9]+}};
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; CHECK: ret;
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%a = fptoui double %x to i16
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ret i16 %a
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}
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define i32 @cvt_i32_f32(float %x) {
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; CHECK: cvt.rzi.u32.f32 %r{{[0-9]+}}, %f{{[0-9]+}};
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; CHECK: ret;
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%a = fptoui float %x to i32
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ret i32 %a
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}
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define i32 @cvt_i32_f64(double %x) {
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; CHECK: cvt.rzi.u32.f64 %r{{[0-9]+}}, %fl{{[0-9]+}};
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; CHECK: ret;
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%a = fptoui double %x to i32
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ret i32 %a
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}
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define i64 @cvt_i64_f32(float %x) {
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; CHECK: cvt.rzi.u64.f32 %rl{{[0-9]+}}, %f{{[0-9]+}};
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; CHECK: ret;
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%a = fptoui float %x to i64
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ret i64 %a
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}
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define i64 @cvt_i64_f64(double %x) {
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; CHECK: cvt.rzi.u64.f64 %rl{{[0-9]+}}, %fl{{[0-9]+}};
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; CHECK: ret;
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%a = fptoui double %x to i64
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ret i64 %a
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}
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define float @cvt_f32_i16(i16 %x) {
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; CHECK: cvt.rn.f32.u16 %f{{[0-9]+}}, %rs{{[0-9]+}};
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; CHECK: ret;
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%a = uitofp i16 %x to float
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ret float %a
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}
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define float @cvt_f32_i32(i32 %x) {
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; CHECK: cvt.rn.f32.u32 %f{{[0-9]+}}, %r{{[0-9]+}};
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; CHECK: ret;
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%a = uitofp i32 %x to float
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ret float %a
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}
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define float @cvt_f32_i64(i64 %x) {
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; CHECK: cvt.rn.f32.u64 %f{{[0-9]+}}, %rl{{[0-9]+}};
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; CHECK: ret;
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%a = uitofp i64 %x to float
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ret float %a
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}
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define float @cvt_f32_f64(double %x) {
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; CHECK: cvt.rn.f32.f64 %f{{[0-9]+}}, %fl{{[0-9]+}};
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; CHECK: ret;
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%a = fptrunc double %x to float
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ret float %a
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}
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define float @cvt_f32_s16(i16 %x) {
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; CHECK: cvt.rn.f32.s16 %f{{[0-9]+}}, %rs{{[0-9]+}}
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; CHECK: ret
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%a = sitofp i16 %x to float
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ret float %a
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}
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define float @cvt_f32_s32(i32 %x) {
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; CHECK: cvt.rn.f32.s32 %f{{[0-9]+}}, %r{{[0-9]+}}
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; CHECK: ret
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%a = sitofp i32 %x to float
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ret float %a
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}
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define float @cvt_f32_s64(i64 %x) {
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; CHECK: cvt.rn.f32.s64 %f{{[0-9]+}}, %rl{{[0-9]+}}
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; CHECK: ret
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%a = sitofp i64 %x to float
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ret float %a
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}
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define double @cvt_f64_i16(i16 %x) {
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; CHECK: cvt.rn.f64.u16 %fl{{[0-9]+}}, %rs{{[0-9]+}};
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; CHECK: ret;
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%a = uitofp i16 %x to double
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ret double %a
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}
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define double @cvt_f64_i32(i32 %x) {
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; CHECK: cvt.rn.f64.u32 %fl{{[0-9]+}}, %r{{[0-9]+}};
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; CHECK: ret;
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%a = uitofp i32 %x to double
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ret double %a
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}
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define double @cvt_f64_i64(i64 %x) {
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; CHECK: cvt.rn.f64.u64 %fl{{[0-9]+}}, %rl{{[0-9]+}};
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; CHECK: ret;
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%a = uitofp i64 %x to double
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ret double %a
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}
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define double @cvt_f64_f32(float %x) {
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; CHECK: cvt.f64.f32 %fl{{[0-9]+}}, %f{{[0-9]+}};
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; CHECK: ret;
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%a = fpext float %x to double
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ret double %a
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}
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define double @cvt_f64_s16(i16 %x) {
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; CHECK: cvt.rn.f64.s16 %fl{{[0-9]+}}, %rs{{[0-9]+}}
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; CHECK: ret
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%a = sitofp i16 %x to double
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ret double %a
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}
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define double @cvt_f64_s32(i32 %x) {
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; CHECK: cvt.rn.f64.s32 %fl{{[0-9]+}}, %r{{[0-9]+}}
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; CHECK: ret
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%a = sitofp i32 %x to double
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ret double %a
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}
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define double @cvt_f64_s64(i64 %x) {
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; CHECK: cvt.rn.f64.s64 %fl{{[0-9]+}}, %rl{{[0-9]+}}
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; CHECK: ret
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%a = sitofp i64 %x to double
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ret double %a
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}
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