llvm-6502/lib/Target/Sparc
Jakob Stoklund Olesen 89f530ebbf Also expand 64-bit bitcasts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-20 01:01:43 +00:00
..
MCTargetDesc Remove unused argument. 2013-05-10 18:16:59 +00:00
TargetInfo Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
CMakeLists.txt llvm/lib: [CMake] Add explicit dependency to intrinsics_gen. 2012-06-24 13:32:01 +00:00
DelaySlotFiller.cpp [Sparc] Prevent instructions that defines or uses %o7 to be in call's delay slot. 2013-05-16 23:53:29 +00:00
FPMover.cpp Use the new script to sort the includes of every file under lib. 2012-12-03 16:50:05 +00:00
LLVMBuild.txt LLVMBuild: Introduce a common section which currently has a list of the 2011-12-12 22:45:54 +00:00
Makefile
README.txt Don't use %g0 to materialize 0 directly. 2013-05-19 21:47:13 +00:00
Sparc.h Fix some leftover control reaches end of non-void function warnings. 2012-01-10 20:47:20 +00:00
Sparc.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcAsmPrinter.cpp Use target flags for printing SPARC asm operands. 2013-04-14 04:35:19 +00:00
SparcCallingConv.td Complete formal arguments for the SPARC v9 64-bit ABI. 2013-04-06 18:32:12 +00:00
SparcFrameLowering.cpp [Sparc] Implements hasReservedCallFrame and hasFP. 2013-05-17 15:14:34 +00:00
SparcFrameLowering.h [Sparc] Implements hasReservedCallFrame and hasFP. 2013-05-17 15:14:34 +00:00
SparcInstr64Bit.td Don't use %g0 to materialize 0 directly. 2013-05-19 21:47:13 +00:00
SparcInstrFormats.td Use i32 for all SPARC shift amounts, even in 64-bit mode. 2013-04-14 05:48:50 +00:00
SparcInstrInfo.cpp Implement spill and fill of I64Regs. 2013-05-20 00:53:25 +00:00
SparcInstrInfo.h Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
SparcInstrInfo.td Implement SPselectfcc for i64 operands. 2013-05-19 20:20:54 +00:00
SparcISelDAGToDAG.cpp Add 64-bit multiply and divide instructions for SPARC v9. 2013-04-16 02:57:02 +00:00
SparcISelLowering.cpp Also expand 64-bit bitcasts. 2013-05-20 01:01:43 +00:00
SparcISelLowering.h Use i32 for all SPARC shift amounts, even in 64-bit mode. 2013-04-14 05:48:50 +00:00
SparcMachineFunctionInfo.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcMachineFunctionInfo.h Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
SparcRegisterInfo.cpp [Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers. 2013-05-19 20:07:20 +00:00
SparcRegisterInfo.h Add an I64Regs register class for 64-bit registers. 2013-04-02 04:08:54 +00:00
SparcRegisterInfo.td [Sparc] Rearrange integer registers' allocation order so that register allocator will use I and G registers before using L and O registers. 2013-05-19 20:07:20 +00:00
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SparcSubtarget.h SPARC v9 stack pointer bias. 2013-04-06 21:38:57 +00:00
SparcTargetMachine.cpp Remove the MachineMove class. 2013-05-13 01:16:13 +00:00
SparcTargetMachine.h Switch TargetTransformInfo from an immutable analysis pass that requires 2013-01-07 01:37:14 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support

* Use %g0 directly to materialize 0. No instruction is required.