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This is the preferred way of creating bundled machine instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169585 91177308-0d34-0410-b5e6-96231b3b80d8
287 lines
8.5 KiB
C++
287 lines
8.5 KiB
C++
//===-- DelaySlotFiller.cpp - Mips Delay Slot Filler ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Simple pass to fills delay slots with useful instructions.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "delay-slot-filler"
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#include "Mips.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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STATISTIC(FilledSlots, "Number of delay slots filled");
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STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that"
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" are not NOP.");
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static cl::opt<bool> DisableDelaySlotFiller(
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"disable-mips-delay-filler",
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cl::init(false),
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cl::desc("Disable the delay slot filler, which attempts to fill the Mips"
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"delay slots with useful instructions."),
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cl::Hidden);
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// This option can be used to silence complaints by machine verifier passes.
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static cl::opt<bool> SkipDelaySlotFiller(
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"skip-mips-delay-filler",
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cl::init(false),
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cl::desc("Skip MIPS' delay slot filling pass."),
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cl::Hidden);
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namespace {
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struct Filler : public MachineFunctionPass {
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typedef MachineBasicBlock::instr_iterator InstrIter;
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typedef MachineBasicBlock::reverse_instr_iterator ReverseInstrIter;
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TargetMachine &TM;
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const TargetInstrInfo *TII;
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InstrIter LastFiller;
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static char ID;
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Filler(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
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virtual const char *getPassName() const {
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return "Mips Delay Slot Filler";
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}
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bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F) {
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if (SkipDelaySlotFiller)
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return false;
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bool Changed = false;
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for (MachineFunction::iterator FI = F.begin(), FE = F.end();
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FI != FE; ++FI)
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Changed |= runOnMachineBasicBlock(*FI);
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return Changed;
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}
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bool isDelayFiller(MachineBasicBlock &MBB,
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InstrIter candidate);
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void insertCallUses(InstrIter MI,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses);
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void insertDefsUses(InstrIter MI,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses);
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bool IsRegInSet(SmallSet<unsigned, 32> &RegSet,
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unsigned Reg);
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bool delayHasHazard(InstrIter candidate,
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bool &sawLoad, bool &sawStore,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses);
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bool
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findDelayInstr(MachineBasicBlock &MBB, InstrIter slot,
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InstrIter &Filler);
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};
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char Filler::ID = 0;
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} // end of anonymous namespace
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/// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
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/// We assume there is only one delay slot per delayed instruction.
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bool Filler::
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runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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LastFiller = MBB.instr_end();
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for (InstrIter I = MBB.instr_begin(); I != MBB.instr_end(); ++I)
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if (I->hasDelaySlot()) {
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++FilledSlots;
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Changed = true;
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InstrIter InstrWithSlot = I;
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InstrIter D;
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// Delay slot filling is disabled at -O0.
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if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None) &&
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findDelayInstr(MBB, I, D)) {
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MBB.splice(llvm::next(I), &MBB, D);
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++UsefulSlots;
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} else
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BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
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// Record the filler instruction that filled the delay slot.
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// The instruction after it will be visited in the next iteration.
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LastFiller = ++I;
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// Bundle the delay slot filler to InstrWithSlot so that the machine
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// verifier doesn't expect this instruction to be a terminator.
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MIBundleBuilder(MBB, InstrWithSlot, llvm::next(LastFiller));
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}
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return Changed;
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}
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/// createMipsDelaySlotFillerPass - Returns a pass that fills in delay
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/// slots in Mips MachineFunctions
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FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) {
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return new Filler(tm);
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}
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bool Filler::findDelayInstr(MachineBasicBlock &MBB,
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InstrIter slot,
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InstrIter &Filler) {
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SmallSet<unsigned, 32> RegDefs;
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SmallSet<unsigned, 32> RegUses;
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insertDefsUses(slot, RegDefs, RegUses);
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bool sawLoad = false;
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bool sawStore = false;
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for (ReverseInstrIter I(slot); I != MBB.instr_rend(); ++I) {
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// skip debug value
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if (I->isDebugValue())
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continue;
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// Convert to forward iterator.
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InstrIter FI(llvm::next(I).base());
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if (I->hasUnmodeledSideEffects()
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|| I->isInlineAsm()
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|| I->isLabel()
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|| FI == LastFiller
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|| I->isPseudo()
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//
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// Should not allow:
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// ERET, DERET or WAIT, PAUSE. Need to add these to instruction
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// list. TBD.
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)
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break;
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if (delayHasHazard(FI, sawLoad, sawStore, RegDefs, RegUses)) {
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insertDefsUses(FI, RegDefs, RegUses);
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continue;
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}
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Filler = FI;
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return true;
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}
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return false;
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}
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bool Filler::delayHasHazard(InstrIter candidate,
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bool &sawLoad, bool &sawStore,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses) {
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if (candidate->isImplicitDef() || candidate->isKill())
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return true;
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// Loads or stores cannot be moved past a store to the delay slot
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// and stores cannot be moved past a load.
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if (candidate->mayLoad()) {
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if (sawStore)
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return true;
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sawLoad = true;
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}
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if (candidate->mayStore()) {
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if (sawStore)
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return true;
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sawStore = true;
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if (sawLoad)
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return true;
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}
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assert((!candidate->isCall() && !candidate->isReturn()) &&
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"Cannot put calls or returns in delay slot.");
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for (unsigned i = 0, e = candidate->getNumOperands(); i!= e; ++i) {
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const MachineOperand &MO = candidate->getOperand(i);
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unsigned Reg;
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if (!MO.isReg() || !(Reg = MO.getReg()))
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continue; // skip
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if (MO.isDef()) {
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// check whether Reg is defined or used before delay slot.
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if (IsRegInSet(RegDefs, Reg) || IsRegInSet(RegUses, Reg))
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return true;
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}
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if (MO.isUse()) {
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// check whether Reg is defined before delay slot.
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if (IsRegInSet(RegDefs, Reg))
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return true;
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}
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}
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return false;
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}
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// Helper function for getting a MachineOperand's register number and adding it
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// to RegDefs or RegUses.
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static void insertDefUse(const MachineOperand &MO,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses,
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unsigned ExcludedReg = 0) {
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unsigned Reg;
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if (!MO.isReg() || !(Reg = MO.getReg()) || (Reg == ExcludedReg))
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return;
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if (MO.isDef())
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RegDefs.insert(Reg);
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else if (MO.isUse())
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RegUses.insert(Reg);
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}
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// Insert Defs and Uses of MI into the sets RegDefs and RegUses.
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void Filler::insertDefsUses(InstrIter MI,
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SmallSet<unsigned, 32> &RegDefs,
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SmallSet<unsigned, 32> &RegUses) {
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unsigned I, E = MI->getDesc().getNumOperands();
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for (I = 0; I != E; ++I)
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insertDefUse(MI->getOperand(I), RegDefs, RegUses);
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// If MI is a call, add RA to RegDefs to prevent users of RA from going into
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// delay slot.
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if (MI->isCall()) {
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RegDefs.insert(Mips::RA);
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return;
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}
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// Return if MI is a return.
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if (MI->isReturn())
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return;
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// Examine the implicit operands. Exclude register AT which is in the list of
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// clobbered registers of branch instructions.
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E = MI->getNumOperands();
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for (; I != E; ++I)
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insertDefUse(MI->getOperand(I), RegDefs, RegUses, Mips::AT);
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}
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//returns true if the Reg or its alias is in the RegSet.
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bool Filler::IsRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) {
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// Check Reg and all aliased Registers.
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for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true);
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AI.isValid(); ++AI)
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if (RegSet.count(*AI))
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return true;
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return false;
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}
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