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Use the new MIBundleBuilder class in the Mips target.
This is the preferred way of creating bundled machine instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169585 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -112,7 +112,7 @@ runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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if (I->hasDelaySlot()) {
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++FilledSlots;
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Changed = true;
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InstrIter InstrWithSlot = I;
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InstrIter D;
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// Delay slot filling is disabled at -O0.
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@ -127,9 +127,9 @@ runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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// The instruction after it will be visited in the next iteration.
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LastFiller = ++I;
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// Set InsideBundle bit so that the machine verifier doesn't expect this
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// instruction to be a terminator.
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LastFiller->setIsInsideBundle();
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// Bundle the delay slot filler to InstrWithSlot so that the machine
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// verifier doesn't expect this instruction to be a terminator.
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MIBundleBuilder(MBB, InstrWithSlot, llvm::next(LastFiller));
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}
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return Changed;
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@ -284,9 +284,10 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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.addReg(Mips::SP).addImm(-8);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
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.addReg(Mips::SP).addImm(0);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi)
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->setIsInsideBundle();
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MIBundleBuilder(*LongBrMBB, Pos)
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.append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
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.append(BuildMI(*MF, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi));
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Pos = BalTgtMBB->begin();
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@ -296,9 +297,11 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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.addReg(Mips::RA).addReg(Mips::AT);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
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.addReg(Mips::SP).addImm(0);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
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.addReg(Mips::SP).addImm(8)->setIsInsideBundle();
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MIBundleBuilder(*BalTgtMBB, Pos)
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.append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
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.append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP)
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.addReg(Mips::SP).addImm(8));
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} else {
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// $longbr:
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// daddiu $sp, $sp, -16
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@ -336,9 +339,11 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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.addReg(Mips::AT_64).addImm(16);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(Hi);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(16)->setIsInsideBundle();
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MIBundleBuilder(*LongBrMBB, Pos)
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.append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
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.append(BuildMI(*MF, DL, TII->get(Mips::DSLL), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(16));
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Pos = BalTgtMBB->begin();
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@ -348,9 +353,11 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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.addReg(Mips::RA_64).addReg(Mips::AT_64);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
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.addReg(Mips::SP_64).addImm(0);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
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.addReg(Mips::SP_64).addImm(16)->setIsInsideBundle();
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MIBundleBuilder(*BalTgtMBB, Pos)
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.append(BuildMI(*MF, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64))
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.append(BuildMI(*MF, DL, TII->get(Mips::DADDiu), Mips::SP_64)
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.addReg(Mips::SP_64).addImm(16));
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}
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assert(BalTgtMBBSize == BalTgtMBB->size());
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@ -363,8 +370,9 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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//
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Pos = LongBrMBB->begin();
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LongBrMBB->addSuccessor(TgtMBB);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::J)).addMBB(TgtMBB);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::NOP))->setIsInsideBundle();
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MIBundleBuilder(*LongBrMBB, Pos)
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.append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
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.append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
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assert(LongBrMBB->size() == LongBranchSeqSize);
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}
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