llvm-6502/test/CodeGen/Mips/eh-return64.ll
Daniel Sanders 7c2ef822f7 [mips][mips64r6] Use JALR for returns instead of JR (which is not available on MIPS32r6/MIPS64r6)
Summary:
RET, and RET_MM have been replaced by a pseudo named PseudoReturn.
In addition a version with a 64-bit GPR named PseudoReturn64 has been
added.

Instruction selection for a return matches RetRA, which is expanded post
register allocation to PseudoReturn/PseudoReturn64. During MipsAsmPrinter,
this PseudoReturn/PseudoReturn64 are emitted as:
- (JALR64 $zero, $rs) on MIPS64r6
- (JALR $zero, $rs) on MIPS32r6
- (JR_MM $rs) on microMIPS
- (JR $rs) otherwise

On MIPS32r6/MIPS64r6, 'jr $rs' is an alias for 'jalr $zero, $rs'. To aid
development and review (specifically, to ensure all cases of jr are
updated), these aliases are temporarily named 'r6.jr' instead of 'jr'.
A follow up patch will change them back to the correct mnemonic.

Added (JALR $zero, $rs) to MipsNaClELFStreamer's definition of an indirect
jump, and removed it from its definition of a call.
Note: I haven't accounted for MIPS64 in MipsNaClELFStreamer since it's
doesn't appear to account for any MIPS64-specifics.

The return instruction created as part of eh_return expansion is now expanded
using expandRetRA() so we use the right return instruction on MIPS32r6/MIPS64r6
('jalr $zero, $rs').

Also, fixed a misuse of isABI_N64() to detect 64-bit wide registers in
expandEhReturn().

Reviewers: jkolek, vmedic, mseaborn, zoran.jovanovic, dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D4268


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-09 10:16:07 +00:00

94 lines
3.4 KiB
LLVM

; RUN: llc -march=mips64el -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
; RUN: llc -march=mips64el -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
; RUN: llc -march=mips64el -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
; RUN: llc -march=mips64el -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=R6
declare void @llvm.eh.return.i64(i64, i8*)
declare void @foo(...)
define void @f1(i64 %offset, i8* %handler) {
entry:
call void (...)* @foo()
call void @llvm.eh.return.i64(i64 %offset, i8* %handler)
unreachable
; CHECK: f1:
; CHECK: daddiu $sp, $sp, -[[spoffset:[0-9]+]]
; check that $a0-$a3 are saved on stack.
; CHECK: sd $4, [[offset0:[0-9]+]]($sp)
; CHECK: sd $5, [[offset1:[0-9]+]]($sp)
; CHECK: sd $6, [[offset2:[0-9]+]]($sp)
; CHECK: sd $7, [[offset3:[0-9]+]]($sp)
; check that .cfi_offset directives are emitted for $a0-$a3.
; CHECK: .cfi_offset 4,
; CHECK: .cfi_offset 5,
; CHECK: .cfi_offset 6,
; CHECK: .cfi_offset 7,
; check that stack adjustment and handler are put in $v1 and $v0.
; CHECK: move $[[R0:[a-z0-9]+]], $5
; CHECK: move $[[R1:[a-z0-9]+]], $4
; CHECK: move $3, $[[R1]]
; CHECK: move $2, $[[R0]]
; check that $a0-$a3 are restored from stack.
; CHECK: ld $4, [[offset0]]($sp)
; CHECK: ld $5, [[offset1]]($sp)
; CHECK: ld $6, [[offset2]]($sp)
; CHECK: ld $7, [[offset3]]($sp)
; check that stack is adjusted by $v1 and that code returns to address in $v0
; also check that $25 contains handler value
; CHECK: daddiu $sp, $sp, [[spoffset]]
; CHECK: move $25, $2
; CHECK: move $ra, $2
; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
; CHECK: daddu $sp, $sp, $3
}
define void @f2(i64 %offset, i8* %handler) {
entry:
call void @llvm.eh.return.i64(i64 %offset, i8* %handler)
unreachable
; CHECK: f2:
; CHECK: .cfi_startproc
; CHECK: daddiu $sp, $sp, -[[spoffset:[0-9]+]]
; CHECK: .cfi_def_cfa_offset [[spoffset]]
; check that $a0-$a3 are saved on stack.
; CHECK: sd $4, [[offset0:[0-9]+]]($sp)
; CHECK: sd $5, [[offset1:[0-9]+]]($sp)
; CHECK: sd $6, [[offset2:[0-9]+]]($sp)
; CHECK: sd $7, [[offset3:[0-9]+]]($sp)
; check that .cfi_offset directives are emitted for $a0-$a3.
; CHECK: .cfi_offset 4, -8
; CHECK: .cfi_offset 5, -16
; CHECK: .cfi_offset 6, -24
; CHECK: .cfi_offset 7, -32
; check that stack adjustment and handler are put in $v1 and $v0.
; CHECK: move $3, $4
; CHECK: move $2, $5
; check that $a0-$a3 are restored from stack.
; CHECK: ld $4, [[offset0]]($sp)
; CHECK: ld $5, [[offset1]]($sp)
; CHECK: ld $6, [[offset2]]($sp)
; CHECK: ld $7, [[offset3]]($sp)
; check that stack is adjusted by $v1 and that code returns to address in $v0
; also check that $25 contains handler value
; CHECK: daddiu $sp, $sp, [[spoffset]]
; CHECK: move $25, $2
; CHECK: move $ra, $2
; NOT-R6: jr $ra # <MCInst #{{[0-9]+}} JR
; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
; CHECK: daddu $sp, $sp, $3
; CHECK: .cfi_endproc
}