Juergen Ributzka cb99212bc1 [FastISel][AArch64] Add select folding support for the XALU intrinsics. ...

This improves the code generation for the XALU intrinsics when the
condition is feeding a select instruction.

This also updates and enables the XALU unit tests for FastISel.

This fixes <rdar://problem/17831117>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214350 91177308-0d34-0410-b5e6-96231b3b80d8

2014-07-30 22:04:37 +00:00

..

AsmParser

Run sort_includes.py on the AArch64 backend.

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Disassembler

Run sort_includes.py on the AArch64 backend.

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InstPrinter

Run sort_includes.py on the AArch64 backend.

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MCTargetDesc

Run sort_includes.py on the AArch64 backend.

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TargetInfo

AArch64: remove "arm64_be" support in favour of "aarch64_be".

2014-07-23 12:58:11 +00:00

Utils

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AArch64.h

Run sort_includes.py on the AArch64 backend.

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AArch64.td

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AArch64AddressTypePromotion.cpp

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AArch64AdvSIMDScalarPass.cpp

Run sort_includes.py on the AArch64 backend.

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AArch64AsmPrinter.cpp

Run sort_includes.py on the AArch64 backend.

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AArch64BranchRelaxation.cpp

Run sort_includes.py on the AArch64 backend.

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AArch64CallingConvention.td

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AArch64CleanupLocalDynamicTLSPass.cpp

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AArch64CollectLOH.cpp

Run sort_includes.py on the AArch64 backend.

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AArch64ConditionalCompares.cpp

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AArch64DeadRegisterDefinitionsPass.cpp

Run sort_includes.py on the AArch64 backend.

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AArch64ExpandPseudoInsts.cpp

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AArch64FastISel.cpp

[FastISel][AArch64] Add select folding support for the XALU intrinsics.

2014-07-30 22:04:37 +00:00

AArch64FrameLowering.cpp

Run sort_includes.py on the AArch64 backend.

2014-07-25 11:42:14 +00:00

AArch64FrameLowering.h

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AArch64InstrAtomics.td

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AArch64InstrFormats.td

Implement AArch64 TTI interface isAsCheapAsAMove.

2014-07-29 02:09:26 +00:00

AArch64InstrInfo.cpp

Implement AArch64 TTI interface isAsCheapAsAMove.

2014-07-29 02:09:26 +00:00

AArch64InstrInfo.h

Implement AArch64 TTI interface isAsCheapAsAMove.

2014-07-29 02:09:26 +00:00

AArch64InstrInfo.td

[AArch64] Disable some optimization cases for type conversion from sint to fp, because those optimization cases are micro-architecture dependent and only make sense for Cyclone. A new predicate Cyclone is introduced in .td file.

2014-07-24 01:29:59 +00:00

AArch64ISelDAGToDAG.cpp

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AArch64ISelLowering.cpp

Add alignment value to allowsUnalignedMemoryAccess

2014-07-27 17:46:40 +00:00

AArch64ISelLowering.h

Add alignment value to allowsUnalignedMemoryAccess

2014-07-27 17:46:40 +00:00

AArch64LoadStoreOptimizer.cpp

Run sort_includes.py on the AArch64 backend.

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AArch64MachineFunctionInfo.h

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AArch64MCInstLower.cpp

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AArch64MCInstLower.h

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AArch64PerfectShuffle.h

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AArch64PromoteConstant.cpp

Run sort_includes.py on the AArch64 backend.

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AArch64RegisterInfo.cpp

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AArch64RegisterInfo.h

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AArch64RegisterInfo.td

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AArch64SchedA53.td

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AArch64SchedA57.td

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AArch64SchedA57WriteRes.td

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AArch64SchedCyclone.td

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AArch64Schedule.td

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AArch64SelectionDAGInfo.cpp

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AArch64SelectionDAGInfo.h

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AArch64StorePairSuppress.cpp

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AArch64Subtarget.cpp

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AArch64Subtarget.h

Implement AArch64 TTI interface isAsCheapAsAMove.

2014-07-29 02:09:26 +00:00

AArch64TargetMachine.cpp

Run sort_includes.py on the AArch64 backend.

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AArch64TargetMachine.h

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AArch64TargetObjectFile.cpp

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AArch64TargetObjectFile.h

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AArch64TargetTransformInfo.cpp

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CMakeLists.txt

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LLVMBuild.txt

Prune redundant libdeps.

2014-07-24 11:45:27 +00:00

Makefile

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