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https://github.com/c64scene-ar/llvm-6502.git
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f73bae1b73
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24513 91177308-0d34-0410-b5e6-96231b3b80d8
937 lines
34 KiB
C++
937 lines
34 KiB
C++
//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that X86 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86ISelLowering.h"
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#include "X86TargetMachine.h"
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#include "llvm/CallingConv.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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// FIXME: temporary.
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#include "llvm/Support/CommandLine.h"
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static cl::opt<bool> EnableFastCC("enable-x86-fastcc", cl::Hidden,
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cl::desc("Enable fastcc on X86"));
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X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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: TargetLowering(TM) {
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// Set up the TargetLowering object.
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// X86 is weird, it always uses i8 for shift amounts and setcc results.
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setShiftAmountType(MVT::i8);
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setSetCCResultType(MVT::i8);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
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// Set up the register classes.
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// FIXME: Eliminate these two classes when legalize can handle promotions
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// well.
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addRegisterClass(MVT::i1, X86::R8RegisterClass);
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addRegisterClass(MVT::i8, X86::R8RegisterClass);
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addRegisterClass(MVT::i16, X86::R16RegisterClass);
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addRegisterClass(MVT::i32, X86::R32RegisterClass);
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// Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
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// operation.
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setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
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setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
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setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
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setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
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// Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
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// this operation.
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setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
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setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
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if (!X86ScalarSSE) {
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// We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
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// isn't legal.
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setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
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setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
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setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
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setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
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}
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// Handle FP_TO_UINT by promoting the destination to a larger signed
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// conversion.
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setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
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setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
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setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
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if (!X86ScalarSSE)
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setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
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// Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
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// this operation.
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setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
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setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
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setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
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setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
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setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
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setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
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setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::FREM , MVT::f64 , Expand);
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setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
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setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
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setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
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setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom);
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setOperationAction(ISD::READIO , MVT::i1 , Expand);
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setOperationAction(ISD::READIO , MVT::i8 , Expand);
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setOperationAction(ISD::READIO , MVT::i16 , Expand);
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setOperationAction(ISD::READIO , MVT::i32 , Expand);
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setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
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setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
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setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
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setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
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// These should be promoted to a larger select which is supported.
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setOperationAction(ISD::SELECT , MVT::i1 , Promote);
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setOperationAction(ISD::SELECT , MVT::i8 , Promote);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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if (X86ScalarSSE) {
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// Set up the FP register classes.
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addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
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addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
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// SSE has no load+extend ops
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setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
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setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
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// SSE has no i16 to fp conversion, only i32
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setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
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setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
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// Expand FP_TO_UINT into a select.
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// FIXME: We would like to use a Custom expander here eventually to do
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// the optimal thing for SSE vs. the default expansion in the legalizer.
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setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
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// We don't support sin/cos/sqrt/fmod
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FABS , MVT::f64, Expand);
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setOperationAction(ISD::FNEG , MVT::f64, Expand);
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setOperationAction(ISD::FREM , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FABS , MVT::f32, Expand);
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setOperationAction(ISD::FNEG , MVT::f32, Expand);
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setOperationAction(ISD::FREM , MVT::f32, Expand);
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addLegalFPImmediate(+0.0); // xorps / xorpd
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} else {
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// Set up the FP register classes.
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addRegisterClass(MVT::f64, X86::RFPRegisterClass);
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if (!UnsafeFPMath) {
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setOperationAction(ISD::FSIN , MVT::f64 , Expand);
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setOperationAction(ISD::FCOS , MVT::f64 , Expand);
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}
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addLegalFPImmediate(+0.0); // FLD0
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addLegalFPImmediate(+1.0); // FLD1
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addLegalFPImmediate(-0.0); // FLD0/FCHS
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addLegalFPImmediate(-1.0); // FLD1/FCHS
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}
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computeRegisterProperties();
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maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
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maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
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maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
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allowUnalignedMemoryAccesses = true; // x86 supports it!
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}
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std::vector<SDOperand>
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X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
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return LowerFastCCArguments(F, DAG);
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return LowerCCCArguments(F, DAG);
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}
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std::pair<SDOperand, SDOperand>
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X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
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bool isVarArg, unsigned CallingConv,
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bool isTailCall,
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SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG) {
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assert((!isVarArg || CallingConv == CallingConv::C) &&
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"Only C takes varargs!");
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if (CallingConv == CallingConv::Fast && EnableFastCC)
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return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
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return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
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}
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//===----------------------------------------------------------------------===//
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// C Calling Convention implementation
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//===----------------------------------------------------------------------===//
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std::vector<SDOperand>
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X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
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std::vector<SDOperand> ArgValues;
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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// Add DAG nodes to load the arguments... On entry to a function on the X86,
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// the stack frame looks like this:
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//
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// [ESP] -- return address
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// [ESP + 4] -- first argument (leftmost lexically)
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// [ESP + 8] -- second argument, if first argument is four bytes in size
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// ...
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//
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unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
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MVT::ValueType ObjectVT = getValueType(I->getType());
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unsigned ArgIncrement = 4;
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unsigned ObjSize;
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8: ObjSize = 1; break;
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case MVT::i16: ObjSize = 2; break;
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case MVT::i32: ObjSize = 4; break;
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case MVT::i64: ObjSize = ArgIncrement = 8; break;
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case MVT::f32: ObjSize = 4; break;
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case MVT::f64: ObjSize = ArgIncrement = 8; break;
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}
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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// Create the SelectionDAG nodes corresponding to a load from this parameter
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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// Don't codegen dead arguments. FIXME: remove this check when we can nuke
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// dead loads.
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SDOperand ArgValue;
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if (!I->use_empty())
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ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
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DAG.getSrcValue(NULL));
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else {
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if (MVT::isInteger(ObjectVT))
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ArgValue = DAG.getConstant(0, ObjectVT);
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else
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ArgValue = DAG.getConstantFP(0, ObjectVT);
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}
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ArgValues.push_back(ArgValue);
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ArgOffset += ArgIncrement; // Move on to the next argument...
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}
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// If the function takes variable number of arguments, make a frame index for
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// the start of the first vararg value... for expansion of llvm.va_start.
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if (F.isVarArg())
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VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
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ReturnAddrIndex = 0; // No return address slot generated yet.
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BytesToPopOnReturn = 0; // Callee pops nothing.
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BytesCallerReserves = ArgOffset;
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// Finally, inform the code generator which regs we return values in.
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switch (getValueType(F.getReturnType())) {
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default: assert(0 && "Unknown type!");
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case MVT::isVoid: break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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MF.addLiveOut(X86::EAX);
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break;
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case MVT::i64:
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MF.addLiveOut(X86::EAX);
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MF.addLiveOut(X86::EDX);
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break;
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case MVT::f32:
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case MVT::f64:
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MF.addLiveOut(X86::ST0);
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break;
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}
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return ArgValues;
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}
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std::pair<SDOperand, SDOperand>
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X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
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bool isVarArg, bool isTailCall,
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SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG) {
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// Count how many bytes are to be pushed on the stack.
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unsigned NumBytes = 0;
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if (Args.empty()) {
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// Save zero bytes.
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Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
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DAG.getConstant(0, getPointerTy()));
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} else {
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for (unsigned i = 0, e = Args.size(); i != e; ++i)
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switch (getValueType(Args[i].second)) {
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default: assert(0 && "Unknown value type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::f32:
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NumBytes += 4;
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break;
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case MVT::i64:
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case MVT::f64:
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NumBytes += 8;
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break;
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}
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Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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// Arguments go on the stack in reverse order, as specified by the ABI.
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unsigned ArgOffset = 0;
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SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
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X86::ESP, MVT::i32);
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std::vector<SDOperand> Stores;
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for (unsigned i = 0, e = Args.size(); i != e; ++i) {
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SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
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PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
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switch (getValueType(Args[i].second)) {
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default: assert(0 && "Unexpected ValueType for argument!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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// Promote the integer to 32 bits. If the input type is signed use a
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// sign extend, otherwise use a zero extend.
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if (Args[i].second->isSigned())
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Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
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else
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Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
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// FALL THROUGH
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case MVT::i32:
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case MVT::f32:
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Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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Args[i].first, PtrOff,
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DAG.getSrcValue(NULL)));
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ArgOffset += 4;
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break;
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case MVT::i64:
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case MVT::f64:
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Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
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Args[i].first, PtrOff,
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DAG.getSrcValue(NULL)));
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ArgOffset += 8;
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break;
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}
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}
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
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}
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std::vector<MVT::ValueType> RetVals;
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MVT::ValueType RetTyVT = getValueType(RetTy);
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RetVals.push_back(MVT::Other);
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// The result values produced have to be legal. Promote the result.
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switch (RetTyVT) {
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case MVT::isVoid: break;
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default:
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RetVals.push_back(RetTyVT);
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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RetVals.push_back(MVT::i32);
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break;
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case MVT::f32:
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if (X86ScalarSSE)
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RetVals.push_back(MVT::f32);
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else
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RetVals.push_back(MVT::f64);
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break;
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case MVT::i64:
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RetVals.push_back(MVT::i32);
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RetVals.push_back(MVT::i32);
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break;
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}
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
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Ops.push_back(DAG.getConstant(0, getPointerTy()));
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SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
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RetVals, Ops);
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Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
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SDOperand ResultVal;
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switch (RetTyVT) {
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case MVT::isVoid: break;
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default:
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ResultVal = TheCall.getValue(1);
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
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break;
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case MVT::f32:
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// FIXME: we would really like to remember that this FP_ROUND operation is
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// okay to eliminate if we allow excess FP precision.
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ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
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break;
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case MVT::i64:
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ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
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TheCall.getValue(2));
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break;
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}
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return std::make_pair(ResultVal, Chain);
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}
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SDOperand
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X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
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Value *VAListV, SelectionDAG &DAG) {
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// vastart just stores the address of the VarArgsFrameIndex slot.
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SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
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return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
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DAG.getSrcValue(VAListV));
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}
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std::pair<SDOperand,SDOperand>
|
|
X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
|
|
Value *VAListV, const Type *ArgTy,
|
|
SelectionDAG &DAG) {
|
|
MVT::ValueType ArgVT = getValueType(ArgTy);
|
|
SDOperand Val = DAG.getLoad(MVT::i32, Chain,
|
|
VAListP, DAG.getSrcValue(VAListV));
|
|
SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
|
|
DAG.getSrcValue(NULL));
|
|
unsigned Amt;
|
|
if (ArgVT == MVT::i32)
|
|
Amt = 4;
|
|
else {
|
|
assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
|
|
"Other types should have been promoted for varargs!");
|
|
Amt = 8;
|
|
}
|
|
Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
|
|
DAG.getConstant(Amt, Val.getValueType()));
|
|
Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
Val, VAListP, DAG.getSrcValue(VAListV));
|
|
return std::make_pair(Result, Chain);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Fast Calling Convention implementation
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// The X86 'fast' calling convention passes up to two integer arguments in
|
|
// registers (an appropriate portion of EAX/EDX), passes arguments in C order,
|
|
// and requires that the callee pop its arguments off the stack (allowing proper
|
|
// tail calls), and has the same return value conventions as C calling convs.
|
|
//
|
|
// This calling convention always arranges for the callee pop value to be 8n+4
|
|
// bytes, which is needed for tail recursion elimination and stack alignment
|
|
// reasons.
|
|
//
|
|
// Note that this can be enhanced in the future to pass fp vals in registers
|
|
// (when we have a global fp allocator) and do other tricks.
|
|
//
|
|
|
|
/// AddLiveIn - This helper function adds the specified physical register to the
|
|
/// MachineFunction as a live in value. It also creates a corresponding virtual
|
|
/// register for it.
|
|
static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
|
|
TargetRegisterClass *RC) {
|
|
assert(RC->contains(PReg) && "Not the correct regclass!");
|
|
unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
|
|
MF.addLiveIn(PReg, VReg);
|
|
return VReg;
|
|
}
|
|
|
|
|
|
std::vector<SDOperand>
|
|
X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
|
|
std::vector<SDOperand> ArgValues;
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
|
|
// Add DAG nodes to load the arguments... On entry to a function the stack
|
|
// frame looks like this:
|
|
//
|
|
// [ESP] -- return address
|
|
// [ESP + 4] -- first nonreg argument (leftmost lexically)
|
|
// [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
|
|
// ...
|
|
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
|
|
|
|
// Keep track of the number of integer regs passed so far. This can be either
|
|
// 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
|
|
// used).
|
|
unsigned NumIntRegs = 0;
|
|
|
|
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
|
|
MVT::ValueType ObjectVT = getValueType(I->getType());
|
|
unsigned ArgIncrement = 4;
|
|
unsigned ObjSize = 0;
|
|
SDOperand ArgValue;
|
|
|
|
switch (ObjectVT) {
|
|
default: assert(0 && "Unhandled argument type!");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
if (NumIntRegs < 2) {
|
|
if (!I->use_empty()) {
|
|
unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
|
|
X86::R8RegisterClass);
|
|
ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
|
|
DAG.setRoot(ArgValue.getValue(1));
|
|
}
|
|
++NumIntRegs;
|
|
break;
|
|
}
|
|
|
|
ObjSize = 1;
|
|
break;
|
|
case MVT::i16:
|
|
if (NumIntRegs < 2) {
|
|
if (!I->use_empty()) {
|
|
unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
|
|
X86::R16RegisterClass);
|
|
ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
|
|
DAG.setRoot(ArgValue.getValue(1));
|
|
}
|
|
++NumIntRegs;
|
|
break;
|
|
}
|
|
ObjSize = 2;
|
|
break;
|
|
case MVT::i32:
|
|
if (NumIntRegs < 2) {
|
|
if (!I->use_empty()) {
|
|
unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
|
|
X86::R32RegisterClass);
|
|
ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
|
|
DAG.setRoot(ArgValue.getValue(1));
|
|
}
|
|
++NumIntRegs;
|
|
break;
|
|
}
|
|
ObjSize = 4;
|
|
break;
|
|
case MVT::i64:
|
|
if (NumIntRegs == 0) {
|
|
if (!I->use_empty()) {
|
|
unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
|
|
unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
|
|
|
|
SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
|
|
SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
|
|
DAG.setRoot(Hi.getValue(1));
|
|
|
|
ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
|
|
}
|
|
NumIntRegs = 2;
|
|
break;
|
|
} else if (NumIntRegs == 1) {
|
|
if (!I->use_empty()) {
|
|
unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
|
|
SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
|
|
DAG.setRoot(Low.getValue(1));
|
|
|
|
// Load the high part from memory.
|
|
// Create the frame index object for this incoming parameter...
|
|
int FI = MFI->CreateFixedObject(4, ArgOffset);
|
|
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
|
|
SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
|
|
DAG.getSrcValue(NULL));
|
|
ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
|
|
}
|
|
ArgOffset += 4;
|
|
NumIntRegs = 2;
|
|
break;
|
|
}
|
|
ObjSize = ArgIncrement = 8;
|
|
break;
|
|
case MVT::f32: ObjSize = 4; break;
|
|
case MVT::f64: ObjSize = ArgIncrement = 8; break;
|
|
}
|
|
|
|
// Don't codegen dead arguments. FIXME: remove this check when we can nuke
|
|
// dead loads.
|
|
if (ObjSize && !I->use_empty()) {
|
|
// Create the frame index object for this incoming parameter...
|
|
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
|
|
|
|
// Create the SelectionDAG nodes corresponding to a load from this
|
|
// parameter.
|
|
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
|
|
|
|
ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
|
|
DAG.getSrcValue(NULL));
|
|
} else if (ArgValue.Val == 0) {
|
|
if (MVT::isInteger(ObjectVT))
|
|
ArgValue = DAG.getConstant(0, ObjectVT);
|
|
else
|
|
ArgValue = DAG.getConstantFP(0, ObjectVT);
|
|
}
|
|
ArgValues.push_back(ArgValue);
|
|
|
|
if (ObjSize)
|
|
ArgOffset += ArgIncrement; // Move on to the next argument.
|
|
}
|
|
|
|
// Make sure the instruction takes 8n+4 bytes to make sure the start of the
|
|
// arguments and the arguments after the retaddr has been pushed are aligned.
|
|
if ((ArgOffset & 7) == 0)
|
|
ArgOffset += 4;
|
|
|
|
VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
|
|
ReturnAddrIndex = 0; // No return address slot generated yet.
|
|
BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
|
|
BytesCallerReserves = 0;
|
|
|
|
// Finally, inform the code generator which regs we return values in.
|
|
switch (getValueType(F.getReturnType())) {
|
|
default: assert(0 && "Unknown type!");
|
|
case MVT::isVoid: break;
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
MF.addLiveOut(X86::EAX);
|
|
break;
|
|
case MVT::i64:
|
|
MF.addLiveOut(X86::EAX);
|
|
MF.addLiveOut(X86::EDX);
|
|
break;
|
|
case MVT::f32:
|
|
case MVT::f64:
|
|
MF.addLiveOut(X86::ST0);
|
|
break;
|
|
}
|
|
return ArgValues;
|
|
}
|
|
|
|
std::pair<SDOperand, SDOperand>
|
|
X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
|
|
bool isTailCall, SDOperand Callee,
|
|
ArgListTy &Args, SelectionDAG &DAG) {
|
|
// Count how many bytes are to be pushed on the stack.
|
|
unsigned NumBytes = 0;
|
|
|
|
// Keep track of the number of integer regs passed so far. This can be either
|
|
// 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
|
|
// used).
|
|
unsigned NumIntRegs = 0;
|
|
|
|
for (unsigned i = 0, e = Args.size(); i != e; ++i)
|
|
switch (getValueType(Args[i].second)) {
|
|
default: assert(0 && "Unknown value type!");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
if (NumIntRegs < 2) {
|
|
++NumIntRegs;
|
|
break;
|
|
}
|
|
// fall through
|
|
case MVT::f32:
|
|
NumBytes += 4;
|
|
break;
|
|
case MVT::i64:
|
|
if (NumIntRegs == 0) {
|
|
NumIntRegs = 2;
|
|
break;
|
|
} else if (NumIntRegs == 1) {
|
|
NumIntRegs = 2;
|
|
NumBytes += 4;
|
|
break;
|
|
}
|
|
|
|
// fall through
|
|
case MVT::f64:
|
|
NumBytes += 8;
|
|
break;
|
|
}
|
|
|
|
// Make sure the instruction takes 8n+4 bytes to make sure the start of the
|
|
// arguments and the arguments after the retaddr has been pushed are aligned.
|
|
if ((NumBytes & 7) == 0)
|
|
NumBytes += 4;
|
|
|
|
Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
|
|
DAG.getConstant(NumBytes, getPointerTy()));
|
|
|
|
// Arguments go on the stack in reverse order, as specified by the ABI.
|
|
unsigned ArgOffset = 0;
|
|
SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
|
|
X86::ESP, MVT::i32);
|
|
NumIntRegs = 0;
|
|
std::vector<SDOperand> Stores;
|
|
std::vector<SDOperand> RegValuesToPass;
|
|
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
|
|
switch (getValueType(Args[i].second)) {
|
|
default: assert(0 && "Unexpected ValueType for argument!");
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
case MVT::i32:
|
|
if (NumIntRegs < 2) {
|
|
RegValuesToPass.push_back(Args[i].first);
|
|
++NumIntRegs;
|
|
break;
|
|
}
|
|
// Fall through
|
|
case MVT::f32: {
|
|
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
|
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
Args[i].first, PtrOff,
|
|
DAG.getSrcValue(NULL)));
|
|
ArgOffset += 4;
|
|
break;
|
|
}
|
|
case MVT::i64:
|
|
if (NumIntRegs < 2) { // Can pass part of it in regs?
|
|
SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
|
|
Args[i].first, DAG.getConstant(1, MVT::i32));
|
|
SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
|
|
Args[i].first, DAG.getConstant(0, MVT::i32));
|
|
RegValuesToPass.push_back(Lo);
|
|
++NumIntRegs;
|
|
if (NumIntRegs < 2) { // Pass both parts in regs?
|
|
RegValuesToPass.push_back(Hi);
|
|
++NumIntRegs;
|
|
} else {
|
|
// Pass the high part in memory.
|
|
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
|
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
Hi, PtrOff, DAG.getSrcValue(NULL)));
|
|
ArgOffset += 4;
|
|
}
|
|
break;
|
|
}
|
|
// Fall through
|
|
case MVT::f64:
|
|
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
|
|
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
|
|
Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
|
|
Args[i].first, PtrOff,
|
|
DAG.getSrcValue(NULL)));
|
|
ArgOffset += 8;
|
|
break;
|
|
}
|
|
}
|
|
if (!Stores.empty())
|
|
Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
|
|
|
|
// Make sure the instruction takes 8n+4 bytes to make sure the start of the
|
|
// arguments and the arguments after the retaddr has been pushed are aligned.
|
|
if ((ArgOffset & 7) == 0)
|
|
ArgOffset += 4;
|
|
|
|
std::vector<MVT::ValueType> RetVals;
|
|
MVT::ValueType RetTyVT = getValueType(RetTy);
|
|
|
|
RetVals.push_back(MVT::Other);
|
|
|
|
// The result values produced have to be legal. Promote the result.
|
|
switch (RetTyVT) {
|
|
case MVT::isVoid: break;
|
|
default:
|
|
RetVals.push_back(RetTyVT);
|
|
break;
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
RetVals.push_back(MVT::i32);
|
|
break;
|
|
case MVT::f32:
|
|
if (X86ScalarSSE)
|
|
RetVals.push_back(MVT::f32);
|
|
else
|
|
RetVals.push_back(MVT::f64);
|
|
break;
|
|
case MVT::i64:
|
|
RetVals.push_back(MVT::i32);
|
|
RetVals.push_back(MVT::i32);
|
|
break;
|
|
}
|
|
|
|
std::vector<SDOperand> Ops;
|
|
Ops.push_back(Chain);
|
|
Ops.push_back(Callee);
|
|
Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
|
|
// Callee pops all arg values on the stack.
|
|
Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
|
|
|
|
// Pass register arguments as needed.
|
|
Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
|
|
|
|
SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
|
|
RetVals, Ops);
|
|
Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
|
|
|
|
SDOperand ResultVal;
|
|
switch (RetTyVT) {
|
|
case MVT::isVoid: break;
|
|
default:
|
|
ResultVal = TheCall.getValue(1);
|
|
break;
|
|
case MVT::i1:
|
|
case MVT::i8:
|
|
case MVT::i16:
|
|
ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
|
|
break;
|
|
case MVT::f32:
|
|
// FIXME: we would really like to remember that this FP_ROUND operation is
|
|
// okay to eliminate if we allow excess FP precision.
|
|
ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
|
|
break;
|
|
case MVT::i64:
|
|
ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
|
|
TheCall.getValue(2));
|
|
break;
|
|
}
|
|
|
|
return std::make_pair(ResultVal, Chain);
|
|
}
|
|
|
|
SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
|
|
if (ReturnAddrIndex == 0) {
|
|
// Set up a frame object for the return address.
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
|
|
}
|
|
|
|
return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
|
|
}
|
|
|
|
|
|
|
|
std::pair<SDOperand, SDOperand> X86TargetLowering::
|
|
LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
|
|
SelectionDAG &DAG) {
|
|
SDOperand Result;
|
|
if (Depth) // Depths > 0 not supported yet!
|
|
Result = DAG.getConstant(0, getPointerTy());
|
|
else {
|
|
SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
|
|
if (!isFrameAddress)
|
|
// Just load the return address
|
|
Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
|
|
DAG.getSrcValue(NULL));
|
|
else
|
|
Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
|
|
DAG.getConstant(4, MVT::i32));
|
|
}
|
|
return std::make_pair(Result, Chain);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// X86 Custom Lowering Hooks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// LowerOperation - Provide custom lowering hooks for some operations.
|
|
///
|
|
SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
|
|
switch (Op.getOpcode()) {
|
|
default: assert(0 && "Should not custom lower this!");
|
|
case ISD::SINT_TO_FP: {
|
|
assert(Op.getValueType() == MVT::f64 &&
|
|
Op.getOperand(0).getValueType() == MVT::i64 &&
|
|
"Unknown SINT_TO_FP to lower!");
|
|
// We lower sint64->FP into a store to a temporary stack slot, followed by a
|
|
// FILD64m node.
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
|
|
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
|
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
|
|
Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
|
|
std::vector<MVT::ValueType> RTs;
|
|
RTs.push_back(MVT::f64);
|
|
RTs.push_back(MVT::Other);
|
|
std::vector<SDOperand> Ops;
|
|
Ops.push_back(Store);
|
|
Ops.push_back(StackSlot);
|
|
return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
|
|
}
|
|
case ISD::FP_TO_SINT: {
|
|
assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
|
|
Op.getOperand(0).getValueType() == MVT::f64 &&
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|
"Unknown FP_TO_SINT to lower!");
|
|
// We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
|
|
// stack slot.
|
|
MachineFunction &MF = DAG.getMachineFunction();
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|
unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
|
|
int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
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|
SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
|
|
|
unsigned Opc;
|
|
switch (Op.getValueType()) {
|
|
default: assert(0 && "Invalid FP_TO_SINT to lower!");
|
|
case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
|
|
case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
|
|
case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
|
|
}
|
|
|
|
// Build the FP_TO_INT*_IN_MEM
|
|
std::vector<SDOperand> Ops;
|
|
Ops.push_back(DAG.getEntryNode());
|
|
Ops.push_back(Op.getOperand(0));
|
|
Ops.push_back(StackSlot);
|
|
SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
|
|
|
|
// Load the result.
|
|
return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
|
|
DAG.getSrcValue(NULL));
|
|
}
|
|
case ISD::READCYCLECOUNTER: {
|
|
std::vector<MVT::ValueType> Tys;
|
|
Tys.push_back(MVT::Other);
|
|
Tys.push_back(MVT::Flag);
|
|
std::vector<SDOperand> Ops;
|
|
Ops.push_back(Op.getOperand(0));
|
|
SDOperand rd = DAG.getNode(X86ISD::RDTSC_DAG, Tys, Ops);
|
|
Ops.clear();
|
|
Ops.push_back(DAG.getCopyFromReg(rd, X86::EAX, MVT::i32, rd.getValue(1)));
|
|
Ops.push_back(DAG.getCopyFromReg(Ops[0].getValue(1), X86::EDX,
|
|
MVT::i32, Ops[0].getValue(2)));
|
|
Ops.push_back(Ops[1].getValue(1));
|
|
Tys[0] = Tys[1] = MVT::i32;
|
|
Tys.push_back(MVT::Other);
|
|
return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
|
|
}
|
|
}
|
|
}
|