mirror of
https://github.com/c64scene-ar/llvm-6502.git
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6f3661fdcd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132777 91177308-0d34-0410-b5e6-96231b3b80d8
470 lines
16 KiB
C++
470 lines
16 KiB
C++
//===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MIPS target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-isel"
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#include "Mips.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetMachine.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Instructions.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
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// instructions for SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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namespace {
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class MipsDAGToDAGISel : public SelectionDAGISel {
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/// TM - Keep a reference to MipsTargetMachine.
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MipsTargetMachine &TM;
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/// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const MipsSubtarget &Subtarget;
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public:
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explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
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SelectionDAGISel(tm),
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TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
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// Pass Name
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virtual const char *getPassName() const {
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return "MIPS DAG->DAG Pattern Instruction Selection";
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}
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private:
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// Include the pieces autogenerated from the target description.
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#include "MipsGenDAGISel.inc"
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/// getTargetMachine - Return a reference to the TargetMachine, casted
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/// to the target-specific type.
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const MipsTargetMachine &getTargetMachine() {
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return static_cast<const MipsTargetMachine &>(TM);
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}
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/// getInstrInfo - Return a reference to the TargetInstrInfo, casted
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/// to the target-specific type.
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const MipsInstrInfo *getInstrInfo() {
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return getTargetMachine().getInstrInfo();
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}
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SDNode *getGlobalBaseReg();
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SDNode *Select(SDNode *N);
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// Complex Pattern.
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bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset);
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SDNode *SelectLoadFp64(SDNode *N);
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SDNode *SelectStoreFp64(SDNode *N);
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// getI32Imm - Return a target constant with the specified
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// value, of type i32.
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inline SDValue getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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};
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// GOT address into a register.
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SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
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unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
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return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode();
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}
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/// ComplexPattern used on MipsInstrInfo
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/// Used on Mips Load/Store instructions
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bool MipsDAGToDAGISel::
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SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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// on PIC code Load GA
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if (TM.getRelocationModel() == Reloc::PIC_) {
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if (Addr.getOpcode() == MipsISD::WrapperPIC) {
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Base = CurDAG->getRegister(Mips::GP, MVT::i32);
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Offset = Addr.getOperand(0);
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return true;
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}
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} else {
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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else if (Addr.getOpcode() == ISD::TargetGlobalTLSAddress) {
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Base = CurDAG->getRegister(Mips::GP, MVT::i32);
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Offset = Addr;
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return true;
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}
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}
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// Addresses of the form FI+const or FI|const
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isInt<16>(CN->getSExtValue())) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0)))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
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else
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
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return true;
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}
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}
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// Operand is a result from an ADD.
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if (Addr.getOpcode() == ISD::ADD) {
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// When loading from constant pools, load the lower address part in
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// the instruction itself. Example, instead of:
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// lui $2, %hi($CPI1_0)
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// addiu $2, $2, %lo($CPI1_0)
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// lwc1 $f0, 0($2)
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// Generate:
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// lui $2, %hi($CPI1_0)
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// lwc1 $f0, %lo($CPI1_0)($2)
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if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
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Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
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Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
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SDValue LoVal = Addr.getOperand(1);
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if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
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Base = Addr.getOperand(0);
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Offset = LoVal.getOperand(0);
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return true;
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}
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}
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}
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, MVT::i32);
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return true;
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}
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SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
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MVT::SimpleValueType NVT =
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N->getValueType(0).getSimpleVT().SimpleTy;
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if (!Subtarget.isMips1() || NVT != MVT::f64)
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return NULL;
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LoadSDNode *LN = cast<LoadSDNode>(N);
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if (LN->getExtensionType() != ISD::NON_EXTLOAD ||
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LN->getAddressingMode() != ISD::UNINDEXED)
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return NULL;
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SDValue Chain = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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SDValue Offset0, Offset1, Base;
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if (!SelectAddr(N1, Offset0, Base) ||
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N1.getValueType() != MVT::i32)
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return NULL;
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MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
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MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
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DebugLoc dl = N->getDebugLoc();
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// The second load should start after for 4 bytes.
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
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Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Offset0))
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Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
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MVT::i32,
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CP->getAlignment(),
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CP->getOffset()+4,
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CP->getTargetFlags());
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else
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return NULL;
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// Choose the offsets depending on the endianess
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if (TM.getTargetData()->isBigEndian())
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std::swap(Offset0, Offset1);
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// Instead of:
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// ldc $f0, X($3)
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// Generate:
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// lwc $f0, X($3)
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// lwc $f1, X+4($3)
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SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
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MVT::Other, Offset0, Base, Chain);
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SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
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dl, NVT), 0);
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SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
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MVT::f64, Undef, SDValue(LD0, 0));
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SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
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MVT::Other, Offset1, Base, SDValue(LD0, 1));
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SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
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MVT::f64, I0, SDValue(LD1, 0));
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ReplaceUses(SDValue(N, 0), I1);
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ReplaceUses(SDValue(N, 1), Chain);
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cast<MachineSDNode>(LD0)->setMemRefs(MemRefs0, MemRefs0 + 1);
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cast<MachineSDNode>(LD1)->setMemRefs(MemRefs0, MemRefs0 + 1);
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return I1.getNode();
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}
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SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
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if (!Subtarget.isMips1() ||
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N->getOperand(1).getValueType() != MVT::f64)
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return NULL;
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SDValue Chain = N->getOperand(0);
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StoreSDNode *SN = cast<StoreSDNode>(N);
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if (SN->isTruncatingStore() || SN->getAddressingMode() != ISD::UNINDEXED)
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return NULL;
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SDValue N1 = N->getOperand(1);
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SDValue N2 = N->getOperand(2);
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SDValue Offset0, Offset1, Base;
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if (!SelectAddr(N2, Offset0, Base) ||
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N1.getValueType() != MVT::f64 ||
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N2.getValueType() != MVT::i32)
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return NULL;
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MachineSDNode::mmo_iterator MemRefs0 = MF->allocateMemRefsArray(1);
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MemRefs0[0] = cast<MemSDNode>(N)->getMemOperand();
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DebugLoc dl = N->getDebugLoc();
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// Get the even and odd part from the f64 register
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SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
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dl, MVT::f32, N1);
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SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
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dl, MVT::f32, N1);
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// The second store should start after for 4 bytes.
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Offset0))
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Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
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else
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return NULL;
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// Choose the offsets depending on the endianess
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if (TM.getTargetData()->isBigEndian())
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std::swap(Offset0, Offset1);
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// Instead of:
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// sdc $f0, X($3)
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// Generate:
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// swc $f0, X($3)
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// swc $f1, X+4($3)
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SDValue Ops0[] = { FPEven, Offset0, Base, Chain };
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Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
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MVT::Other, Ops0, 4), 0);
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cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
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SDValue Ops1[] = { FPOdd, Offset1, Base, Chain };
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Chain = SDValue(CurDAG->getMachineNode(Mips::SWC1, dl,
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MVT::Other, Ops1, 4), 0);
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cast<MachineSDNode>(Chain.getNode())->setMemRefs(MemRefs0, MemRefs0 + 1);
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ReplaceUses(SDValue(N, 0), Chain);
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return Chain.getNode();
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}
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/// Select instructions not customized! Used for
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/// expanded, promoted and normal instructions
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SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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DebugLoc dl = Node->getDebugLoc();
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// Dump information about the Node being selected
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DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
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// If we have a custom node, we already have selected!
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if (Node->isMachineOpcode()) {
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DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
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return NULL;
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}
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///
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// Instruction Selection not handled by the auto-generated
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// tablegen selection should be handled here.
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///
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switch(Opcode) {
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default: break;
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case ISD::SUBE:
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case ISD::ADDE: {
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SDValue InFlag = Node->getOperand(2), CmpLHS;
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unsigned Opc = InFlag.getOpcode(); (void)Opc;
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assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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(Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
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"(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
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unsigned MOp;
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if (Opcode == ISD::ADDE) {
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CmpLHS = InFlag.getValue(0);
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MOp = Mips::ADDu;
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} else {
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CmpLHS = InFlag.getOperand(0);
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MOp = Mips::SUBu;
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}
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SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
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SDValue LHS = Node->getOperand(0);
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SDValue RHS = Node->getOperand(1);
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EVT VT = LHS.getValueType();
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SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
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SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
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SDValue(Carry,0), RHS);
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return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
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LHS, SDValue(AddCarry,0));
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}
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/// Mul with two results
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case ISD::SMUL_LOHI:
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case ISD::UMUL_LOHI: {
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SDValue Op1 = Node->getOperand(0);
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SDValue Op2 = Node->getOperand(1);
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unsigned Op;
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Op = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
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SDNode *Mul = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
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SDValue InFlag = SDValue(Mul, 0);
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SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
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MVT::Glue, InFlag);
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InFlag = SDValue(Lo,1);
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SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
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if (!SDValue(Node, 0).use_empty())
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ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
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if (!SDValue(Node, 1).use_empty())
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ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
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return NULL;
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}
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/// Special Muls
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case ISD::MUL:
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if (Subtarget.isMips32())
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break;
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case ISD::MULHS:
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case ISD::MULHU: {
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SDValue MulOp1 = Node->getOperand(0);
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SDValue MulOp2 = Node->getOperand(1);
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unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
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SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
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MVT::Glue, MulOp1, MulOp2);
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SDValue InFlag = SDValue(MulNode, 0);
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if (Opcode == ISD::MUL)
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return CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32, InFlag);
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else
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return CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
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}
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// Get target GOT address.
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case ISD::GLOBAL_OFFSET_TABLE:
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return getGlobalBaseReg();
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case ISD::ConstantFP: {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
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if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
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SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
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Mips::ZERO, MVT::i32);
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SDValue Undef = SDValue(
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CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
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SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
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SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
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MVT::f64, Undef, SDValue(MTC, 0));
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SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
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MVT::f64, I0, SDValue(MTC, 0));
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ReplaceUses(SDValue(Node, 0), I1);
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return I1.getNode();
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}
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break;
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}
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case ISD::LOAD:
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if (SDNode *ResNode = SelectLoadFp64(Node))
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return ResNode;
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// Other cases are autogenerated.
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break;
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case ISD::STORE:
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if (SDNode *ResNode = SelectStoreFp64(Node))
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return ResNode;
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// Other cases are autogenerated.
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break;
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case MipsISD::ThreadPointer: {
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unsigned SrcReg = Mips::HWR29;
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unsigned DestReg = Mips::V1;
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SDNode *Rdhwr = CurDAG->getMachineNode(Mips::RDHWR, Node->getDebugLoc(),
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Node->getValueType(0), CurDAG->getRegister(SrcReg, MVT::i32));
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SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg,
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SDValue(Rdhwr, 0));
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SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, MVT::i32);
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ReplaceUses(SDValue(Node, 0), ResNode);
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return ResNode.getNode();
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}
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}
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// Select the default instruction
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SDNode *ResNode = SelectCode(Node);
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DEBUG(errs() << "=> ");
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if (ResNode == NULL || ResNode == Node)
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DEBUG(Node->dump(CurDAG));
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else
|
|
DEBUG(ResNode->dump(CurDAG));
|
|
DEBUG(errs() << "\n");
|
|
return ResNode;
|
|
}
|
|
|
|
/// createMipsISelDag - This pass converts a legalized DAG into a
|
|
/// MIPS-specific DAG, ready for instruction scheduling.
|
|
FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
|
|
return new MipsDAGToDAGISel(TM);
|
|
}
|