Juergen Ributzka d3a04223e8 [FastISel][AArch64] Fix load/store with frame indices. ... At higher optimization levels the LLVM IR may contain more complex patterns for loads/stores from/to frame indices. The 'computeAddress' function wasn't able to handle this and triggered an assertion. This fix extends the possible addressing modes for frame indices. This fixes rdar://problem/18783298. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220700 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-27 18:21:58 +00:00
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AArch64	[FastISel][AArch64] Fix load/store with frame indices.	2014-10-27 18:21:58 +00:00
ARM	[ARM] Select VMAXNM and VMINNM regardless of operand order	2014-10-27 09:23:02 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] For N32/N64, structs must be passed in the upper bits of a register.	2014-10-24 13:09:19 +00:00
MSP430
NVPTX	[NVPTX] aligned byte-buffers for vector return types	2014-10-25 03:46:16 +00:00
PowerPC	[PATCH] Support select-cc for VSFRC when VSX is enabled	2014-10-22 16:58:20 +00:00
R600	R600/SI: Add another failing testcase for i1 copies	2014-10-22 05:30:42 +00:00
SPARC
SystemZ
Thumb
Thumb2
X86	[X86][SSE] Bitcast assertion in XFormVExtractWithShuffleIntoLoad	2014-10-24 21:04:41 +00:00
XCore