Andrew Trick d3a7486ef3 misched: add DAG edges from vreg defs to ExitSU. ... These edges are not really necessary, but it is consistent with the way we currently create physreg edges. Scheduler heuristics that expect a DAG edge to the block terminator could benefit from this change. Although in the future I hope we have a better mechanism for modeling latency across scheduling regions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152895 91177308-0d34-0410-b5e6-96231b3b80d8		2012-03-16 05:04:25 +00:00
..
Analysis	LSR fix: Add isSimplifiedLoopNest to IVUsers analysis.	2012-03-16 03:16:56 +00:00
Archive	Avoid using an invalidated iterator.	2012-01-23 05:07:16 +00:00
AsmParser	Convert assert(0) to llvm_unreachable	2012-02-07 05:05:23 +00:00
Bitcode	llvm::SwitchInst	2012-03-11 06:09:17 +00:00
CodeGen	misched: add DAG edges from vreg defs to ExitSU.	2012-03-16 05:04:25 +00:00
DebugInfo	More dead code removal (using -Wunreachable-code)	2012-01-20 21:51:11 +00:00
ExecutionEngine	Add profiling support for Intel Parallel Amplifier XE (VTune) for JITted code in LLVM.	2012-03-13 08:33:15 +00:00
Linker	Include cctype for isdigit. Patch by Stephen Hines.	2012-03-03 09:36:58 +00:00
MC	Implement relocation-overflow behavior for PE/COFF.	2012-03-15 09:03:03 +00:00
Object	Fix bug found by warning.	2012-03-15 17:49:29 +00:00
Support	Move APInt::operator[] inline.	2012-03-14 00:38:15 +00:00
TableGen	Fix infinite loop in nested multiclasses.	2012-03-07 16:39:35 +00:00
Target	ARM optional operand on MRC/MCR assembly instructions.	2012-03-16 00:45:58 +00:00
Transforms	LSR fix: Add isSimplifiedLoopNest to IVUsers analysis.	2012-03-16 03:16:56 +00:00
VMCore	Extend the inline cost calculation to account for bonuses due to	2012-03-14 23:19:53 +00:00
CMakeLists.txt	Move TableGen's parser and entry point into a library	2011-10-01 16:41:13 +00:00
LLVMBuild.txt	LLVMBuild: Introduce a common section which currently has a list of the	2011-12-12 22:45:54 +00:00
Makefile	Remove more of llvmc and dependencies.	2011-09-20 00:34:27 +00:00