llvm-6502/include/llvm/CodeGen
Arnold Schwaighofer d42730dc71 IfConverter: Use TargetSchedule for instruction latencies
For targets that have instruction itineraries this means no change. Targets
that move over to the new schedule model will use be able the new schedule
module for instruction latencies in the if-converter (the logic is such that if
there is no itineary we will use the new sched model for the latencies).

Before, we queried "TTI->getInstructionLatency()" for the instruction latency
and the extra prediction cost. Now, we query the TargetSchedule abstraction for
the instruction latency and TargetInstrInfo for the extra predictation cost. The
TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if
an itinerary exists, otherwise it will use the new schedule model.

ATTENTION: Out of tree targets!

(I will also send out an email later to LLVMDev)

This means, if your target implements

 unsigned getInstrLatency(const InstrItineraryData *ItinData,
                          const MachineInstr *MI,
                          unsigned *PredCost);

and returns a value for "PredCost", you now also need to implement

 unsigned getPredictationCost(const MachineInstr *MI);

(if your target uses the IfConversion.cpp pass)

radar://15077010

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191671 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-30 15:28:56 +00:00
..
PBQP
Analysis.h [stackprotector] Refactor out the end of isInTailCallPosition into the function returnTypeIsEligibleForTailCall. 2013-08-20 08:36:50 +00:00
AsmPrinter.h Add an instruction deprecation feature to TableGen. 2013-09-12 10:28:05 +00:00
CalcSpillWeights.h
CallingConvLower.h Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 2013-07-14 04:42:23 +00:00
CommandFlags.h Use function attributes to indicate that we don't want to realign the stack. 2013-08-01 21:42:05 +00:00
DAGCombine.h
DFAPacketizer.h
EdgeBundles.h
FastISel.h
FunctionLoweringInfo.h
GCMetadata.h
GCMetadataPrinter.h
GCs.h
GCStrategy.h
IntrinsicLowering.h
ISDOpcodes.h [ARM] Use the load-acquire/store-release instructions optimally in AArch32. 2013-09-26 12:22:36 +00:00
JITCodeEmitter.h
LatencyPriorityQueue.h
LexicalScopes.h
LinkAllAsmWriterComponents.h
LinkAllCodegenComponents.h
LiveInterval.h Even more spelling fixes for "instruction". 2013-09-28 13:42:22 +00:00
LiveIntervalAnalysis.h Auto-compute live intervals on demand. 2013-08-14 23:50:16 +00:00
LiveIntervalUnion.h
LiveRangeEdit.h Auto-compute live intervals on demand. 2013-08-14 23:50:16 +00:00
LiveRegMatrix.h
LiveStackAnalysis.h
LiveVariables.h
MachineBasicBlock.h Even more spelling fixes for "instruction". 2013-09-28 13:42:22 +00:00
MachineBlockFrequencyInfo.h
MachineBranchProbabilityInfo.h Add editor C++ filetype declaration no functionality change. 2013-08-12 21:10:23 +00:00
MachineCodeEmitter.h
MachineCodeInfo.h
MachineConstantPool.h
MachineDominators.h
MachineFrameInfo.h
MachineFunction.h
MachineFunctionAnalysis.h
MachineFunctionPass.h
MachineInstr.h simplify expression 2013-09-17 00:15:33 +00:00
MachineInstrBuilder.h
MachineInstrBundle.h
MachineJumpTableInfo.h
MachineLoopInfo.h
MachineMemOperand.h
MachineModuleInfo.h Make a few more things const. 2013-08-15 20:25:44 +00:00
MachineModuleInfoImpls.h
MachineOperand.h
MachinePassRegistry.h
MachinePostDominators.h
MachineRegisterInfo.h Add a convenient PSetIterator for visiting pressure sets affected by a register. 2013-08-23 17:48:46 +00:00
MachineRelocation.h [typo] An LLVM. 2013-08-16 23:30:19 +00:00
MachineScheduler.h Allow subtarget selection of the default MachineScheduler and document the interface. 2013-09-20 05:14:41 +00:00
MachineSSAUpdater.h
MachineTraceMetrics.h
MachORelocation.h
Passes.h Allow subtarget selection of the default MachineScheduler and document the interface. 2013-09-20 05:14:41 +00:00
PseudoSourceValue.h [typo] An LLVM. 2013-08-16 23:30:19 +00:00
RegAllocPBQP.h
RegAllocRegistry.h
RegisterClassInfo.h
RegisterPressure.h mi-sched: cleanup register pressure update, remove a FIXME. 2013-09-06 17:32:47 +00:00
RegisterScavenging.h
ResourcePriorityQueue.h
RuntimeLibcalls.h [stackprotector] Add in the stackprotector libcall. 2013-08-12 18:45:38 +00:00
ScheduleDAG.h
ScheduleDAGInstrs.h Even more spelling fixes for "instruction". 2013-09-28 13:42:22 +00:00
ScheduleDFS.h
ScheduleHazardRecognizer.h
SchedulerRegistry.h
ScoreboardHazardRecognizer.h
SelectionDAG.h [ARM] Use the load-acquire/store-release instructions optimally in AArch32. 2013-09-26 12:22:36 +00:00
SelectionDAGISel.h
SelectionDAGNodes.h Remove an old workaround for a compiler that EOL'd years ago. 2013-09-29 19:39:02 +00:00
SlotIndexes.h Down-scale slot index distance to save bits. 2013-07-30 19:59:19 +00:00
StackProtector.h [stackprotector] Refactor the StackProtector pass from a single .cpp file into StackProtector.h and StackProtector.cpp. 2013-09-27 21:58:43 +00:00
TargetLoweringObjectFileImpl.h
TargetSchedule.h IfConverter: Use TargetSchedule for instruction latencies 2013-09-30 15:28:56 +00:00
ValueTypes.h Initial support for Neon scalar instructions. 2013-09-24 02:47:27 +00:00
ValueTypes.td Initial support for Neon scalar instructions. 2013-09-24 02:47:27 +00:00
VirtRegMap.h