Andrew Trick d49ffe8284 Teach Thumb2 isel to fold and->rotr ==> ROR. ...

Generalization of Nate Begeman's patch!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130502 91177308-0d34-0410-b5e6-96231b3b80d8

2011-04-29 14:18:15 +00:00

..

Alpha

If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.

2010-12-06 22:39:26 +00:00

ARM

Revert r130454; apparently this doesn't actually work.

2011-04-28 23:55:14 +00:00

Blackfin

Don't completely eliminate identity copies that also modify super register liveness.

2011-03-31 17:55:25 +00:00

CBackend

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CellSPU

don't test for codegen of 'store undef'

2011-04-09 02:31:26 +00:00

CPP

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Generic

Un-XFAIL this test for ARM. <rdar://problem/7662569>

2011-04-20 21:47:45 +00:00

MBlaze

Add scheduling information for the MBlaze backend.

2011-04-11 22:31:52 +00:00

Mips

Lower BlockAddress node when relocation-model is static.

2011-04-25 17:10:45 +00:00

MSP430

Enhance ComputeMaskedBits to know that aligned frameindexes

2011-02-13 22:25:43 +00:00

PowerPC

These tests no longer require linear scan because reserved register coalescing is now universal.

2011-04-05 21:40:41 +00:00

PTX

PTX: support for bitwise operations on predicates

2011-04-28 00:19:51 +00:00

SPARC

These tests no longer require linear scan because reserved register coalescing is now universal.

2011-04-05 21:40:41 +00:00

SystemZ

Fix SystemZ tests

2011-03-31 23:02:12 +00:00

Thumb

Be careful about scheduling nodes above previous calls. It increase usages of

2011-04-26 21:31:35 +00:00

Thumb2

Teach Thumb2 isel to fold and->rotr ==> ROR.

2011-04-29 14:18:15 +00:00

X86

fast-isel sret calls, try 2. We actually do need to do something on x86-32. rdar://problem/9303592 .

2011-04-28 20:19:12 +00:00

XCore

Fix Mips, Sparc, and XCore tests that were dependent on register allocation.

2011-03-31 18:42:43 +00:00