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76fc2d077f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182129 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
952 B
LLVM
25 lines
952 B
LLVM
; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
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; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600-CHECK %s
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; The earliest R600 GPUs have a slightly different encoding than the rest of
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; the VLIW4/5 GPUs.
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; EG-CHECK: @test
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; EG-CHECK: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}]
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; R600-CHECK: @test
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; R600-CHECK: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}]
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define void @test() {
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entry:
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%0 = call float @llvm.R600.load.input(i32 0)
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%1 = call float @llvm.R600.load.input(i32 1)
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%2 = fmul float %0, %1
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call void @llvm.AMDGPU.store.output(float %2, i32 0)
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ret void
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}
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declare float @llvm.R600.load.input(i32) readnone
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declare void @llvm.AMDGPU.store.output(float, i32)
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