Richard Sandiford d50bcb2162 [SystemZ] Register compare-and-branch support ... This patch adds support for the CRJ and CGRJ instructions. Support for the immediate forms will be a separate patch. The architecture has a large number of comparison instructions. I think it's generally better to concentrate on using the "best" comparison instruction first and foremost, then only use something like CRJ if CR really was the natual choice of comparison instruction. The patch therefore opportunistically converts separate CR and BRC instructions into a single CRJ while emitting instructions in ISelLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182764 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-28 10:41:11 +00:00
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AArch64	AArch64: implement ETMv4 trace system registers.	2013-04-03 12:31:29 +00:00
ARM	VSTn instructions have a number of encoding constraints which are not implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review).	2013-05-20 14:57:05 +00:00
MBlaze	Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu	2012-03-25 09:02:19 +00:00
Mips	[mips] DSP-ASE move from HI/LO register instructions.	2013-04-18 00:52:44 +00:00
SystemZ	[SystemZ] Register compare-and-branch support	2013-05-28 10:41:11 +00:00
X86	Add CLAC/STAC instruction encoding/decoding support	2013-04-11 04:52:28 +00:00
XCore	[XCore] Add LDAPB instructions.	2013-05-05 13:36:53 +00:00