Tim Northover d59fc0af0a ARM: relax the atomic release barrier to "dmb ishst" ... I believe the full "dmb ish" barrier is not required to guarantee release semantics for atomic operations. The weaker "dmb ishst" prevents previous operations being reordered with a store executed afterwards, which is enough. A key point to note (fortunately already correct) is that this barrier alone is *insufficient* for sequential consistency, no matter how liberally placed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185339 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-01 14:48:48 +00:00
..
AArch64	AArch64: remove accidental test output file.	2013-06-18 21:16:53 +00:00
ARM	ARM: relax the atomic release barrier to "dmb ishst"	2013-07-01 14:48:48 +00:00
CPP
Generic	Debug Info: clean up usage of Verify.	2013-06-28 05:43:10 +00:00
Hexagon
Inputs
MBlaze
Mips	[mips] Improve code generation for constant multiplication using shifts, adds and	2013-06-26 18:48:17 +00:00
MSP430
NVPTX	[NVPTX] Add support for module-scope inline asm	2013-07-01 13:00:14 +00:00
PowerPC	PPC: Ignore spill/restore requests for VRSAVE (except on Darwin)	2013-06-28 22:29:56 +00:00
R600	R600: Support schedule and packetization of trans-only inst	2013-06-29 19:32:43 +00:00
SI
SPARC	Switch spill weights from a basic loop depth estimation to BlockFrequencyInfo.	2013-06-17 19:00:36 +00:00
SystemZ	[SystemZ] Fix some embarrassing test typos	2013-06-27 09:49:34 +00:00
Thumb
Thumb2	ARM: allow predicated barriers in Thumb mode	2013-06-26 16:52:32 +00:00
X86	Debug Info: clean up usage of Verify.	2013-06-28 05:43:10 +00:00
XCore