mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-28 04:29:44 +00:00
a7603982db
The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
24 lines
970 B
LLVM
24 lines
970 B
LLVM
; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2dsp | FileCheck %s
|
|
|
|
define i32 @smulhi(i32 %x, i32 %y) {
|
|
; CHECK: smulhi
|
|
; CHECK: smmul r0, r1, r0
|
|
%tmp = sext i32 %x to i64 ; <i64> [#uses=1]
|
|
%tmp1 = sext i32 %y to i64 ; <i64> [#uses=1]
|
|
%tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
|
|
%tmp3 = lshr i64 %tmp2, 32 ; <i64> [#uses=1]
|
|
%tmp3.upgrd.1 = trunc i64 %tmp3 to i32 ; <i32> [#uses=1]
|
|
ret i32 %tmp3.upgrd.1
|
|
}
|
|
|
|
define i32 @umulhi(i32 %x, i32 %y) {
|
|
; CHECK: umulhi
|
|
; CHECK: umull r1, r0, r1, r0
|
|
%tmp = zext i32 %x to i64 ; <i64> [#uses=1]
|
|
%tmp1 = zext i32 %y to i64 ; <i64> [#uses=1]
|
|
%tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1]
|
|
%tmp3 = lshr i64 %tmp2, 32 ; <i64> [#uses=1]
|
|
%tmp3.upgrd.2 = trunc i64 %tmp3 to i32 ; <i32> [#uses=1]
|
|
ret i32 %tmp3.upgrd.2
|
|
}
|