mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 03:29:22 +00:00
9985f9f61e
patch by Lauro bug fixed by me git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32795 91177308-0d34-0410-b5e6-96231b3b80d8
363 lines
14 KiB
TableGen
363 lines
14 KiB
TableGen
//===- ARMInstrInfo.td - Target Description for ARM Target ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the "Instituto Nokia de Tecnologia" and
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// is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the ARM instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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// Address operands
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def op_addr_mode1 : Operand<iPTR> {
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let PrintMethod = "printAddrMode1";
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let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
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}
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def op_addr_mode2 : Operand<iPTR> {
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let PrintMethod = "printAddrMode2";
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let MIOperandInfo = (ops ptr_rc, i32imm);
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}
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def op_addr_mode5 : Operand<iPTR> {
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let PrintMethod = "printAddrMode5";
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let MIOperandInfo = (ops ptr_rc, i32imm);
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}
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// Define ARM specific addressing mode.
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//Addressing Mode 1: data processing operands
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def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl],
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[]>;
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//Addressing Mode 2: Load and Store Word or Unsigned Byte
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def addr_mode2 : ComplexPattern<iPTR, 2, "SelectAddrMode2", [], []>;
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//Addressing Mode 5: VFP load/store
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def addr_mode5 : ComplexPattern<iPTR, 2, "SelectAddrMode5", [], []>;
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//===----------------------------------------------------------------------===//
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// Instruction Class Templates
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//===----------------------------------------------------------------------===//
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class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction {
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let Namespace = "ARM";
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dag OperandList = ops;
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let AsmString = asmstr;
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let Pattern = pattern;
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}
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class IntBinOp<string OpcStr, SDNode OpNode> :
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InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
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!strconcat(OpcStr, " $dst, $a, $b"),
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[(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>;
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class FPBinOp<string OpcStr, SDNode OpNode> :
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InstARM<(ops FPRegs:$dst, FPRegs:$a, FPRegs:$b),
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!strconcat(OpcStr, " $dst, $a, $b"),
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[(set FPRegs:$dst, (OpNode FPRegs:$a, FPRegs:$b))]>;
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class DFPBinOp<string OpcStr, SDNode OpNode> :
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InstARM<(ops DFPRegs:$dst, DFPRegs:$a, DFPRegs:$b),
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!strconcat(OpcStr, " $dst, $a, $b"),
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[(set DFPRegs:$dst, (OpNode DFPRegs:$a, DFPRegs:$b))]>;
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class FPUnaryOp<string OpcStr, SDNode OpNode> :
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InstARM<(ops FPRegs:$dst, FPRegs:$src),
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!strconcat(OpcStr, " $dst, $src"),
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[(set FPRegs:$dst, (OpNode FPRegs:$src))]>;
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class DFPUnaryOp<string OpcStr, SDNode OpNode> :
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InstARM<(ops DFPRegs:$dst, DFPRegs:$src),
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!strconcat(OpcStr, " $dst, $src"),
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[(set DFPRegs:$dst, (OpNode DFPRegs:$src))]>;
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class Addr1BinOp<string OpcStr, SDNode OpNode> :
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InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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!strconcat(OpcStr, " $dst, $a, $b"),
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[(set IntRegs:$dst, (OpNode IntRegs:$a, addr_mode1:$b))]>;
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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def brtarget : Operand<OtherVT>;
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// Operand for printing out a condition code.
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let PrintMethod = "printCCOperand" in
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def CCOp : Operand<i32>;
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def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
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def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_ARMCallSeq,
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[SDNPHasChain, SDNPOutFlag]>;
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def SDT_ARMcall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
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def ARMcall : SDNode<"ARMISD::CALL", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def retflag : SDNode<"ARMISD::RET_FLAG", SDTRet,
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[SDNPHasChain, SDNPOptInFlag]>;
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def SDTarmselect : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]>;
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def armselect : SDNode<"ARMISD::SELECT", SDTarmselect, [SDNPInFlag, SDNPOutFlag]>;
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def SDTarmfmstat : SDTypeProfile<0, 0, []>;
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def armfmstat : SDNode<"ARMISD::FMSTAT", SDTarmfmstat, [SDNPInFlag, SDNPOutFlag]>;
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def SDTarmbr : SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
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def armbr : SDNode<"ARMISD::BR", SDTarmbr, [SDNPHasChain, SDNPInFlag, SDNPOutFlag]>;
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def SDTVoidBinOp : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
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def armcmp : SDNode<"ARMISD::CMP", SDTVoidBinOp, [SDNPOutFlag]>;
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def armfsitos : SDNode<"ARMISD::FSITOS", SDTUnaryOp>;
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def armftosis : SDNode<"ARMISD::FTOSIS", SDTUnaryOp>;
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def armfsitod : SDNode<"ARMISD::FSITOD", SDTUnaryOp>;
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def armftosid : SDNode<"ARMISD::FTOSID", SDTUnaryOp>;
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def armfuitos : SDNode<"ARMISD::FUITOS", SDTUnaryOp>;
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def armftouis : SDNode<"ARMISD::FTOUIS", SDTUnaryOp>;
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def armfuitod : SDNode<"ARMISD::FUITOD", SDTUnaryOp>;
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def armftouid : SDNode<"ARMISD::FTOUID", SDTUnaryOp>;
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def SDTarmfmrrd : SDTypeProfile<0, 3, [SDTCisInt<0>, SDTCisInt<1>, SDTCisFP<2>]>;
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def armfmrrd : SDNode<"ARMISD::FMRRD", SDTarmfmrrd,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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def SDTarmfmdrr : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisInt<1>, SDTCisInt<2>]>;
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def armfmdrr : SDNode<"ARMISD::FMDRR", SDTarmfmdrr, []>;
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def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
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"!ADJCALLSTACKUP $amt",
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[(callseq_end imm:$amt)]>, Imp<[R13],[R13]>;
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def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
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"!ADJCALLSTACKDOWN $amt",
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[(callseq_start imm:$amt)]>, Imp<[R13],[R13]>;
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def IMPLICIT_DEF_Int : InstARM<(ops IntRegs:$dst),
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"@IMPLICIT_DEF $dst",
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[(set IntRegs:$dst, (undef))]>;
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def IMPLICIT_DEF_FP : InstARM<(ops FPRegs:$dst), "@IMPLICIT_DEF $dst",
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[(set FPRegs:$dst, (undef))]>;
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def IMPLICIT_DEF_DFP : InstARM<(ops DFPRegs:$dst), "@IMPLICIT_DEF $dst",
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[(set DFPRegs:$dst, (undef))]>;
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let isReturn = 1 in {
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def bx: InstARM<(ops), "bx r14", [(retflag)]>;
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}
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let noResults = 1, Defs = [R0, R1, R2, R3, R14] in {
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def bl: InstARM<(ops i32imm:$func, variable_ops), "bl $func", []>;
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def blx : InstARM<(ops IntRegs:$func, variable_ops), "blx $func", [(ARMcall IntRegs:$func)]>;
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}
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def LDR : InstARM<(ops IntRegs:$dst, op_addr_mode2:$addr),
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"ldr $dst, $addr",
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[(set IntRegs:$dst, (load addr_mode2:$addr))]>;
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def LDRB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
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"ldrb $dst, [$addr]",
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[(set IntRegs:$dst, (zextloadi8 IntRegs:$addr))]>;
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def LDRSB : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
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"ldrsb $dst, [$addr]",
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[(set IntRegs:$dst, (sextloadi8 IntRegs:$addr))]>;
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def LDRH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
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"ldrh $dst, [$addr]",
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[(set IntRegs:$dst, (zextloadi16 IntRegs:$addr))]>;
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def LDRSH : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
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"ldrsh $dst, [$addr]",
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[(set IntRegs:$dst, (sextloadi16 IntRegs:$addr))]>;
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def STR : InstARM<(ops IntRegs:$src, op_addr_mode2:$addr),
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"str $src, $addr",
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[(store IntRegs:$src, addr_mode2:$addr)]>;
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def STRB : InstARM<(ops IntRegs:$src, IntRegs:$addr),
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"strb $src, [$addr]",
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[(truncstorei8 IntRegs:$src, IntRegs:$addr)]>;
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def STRH : InstARM<(ops IntRegs:$src, IntRegs:$addr),
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"strh $src, [$addr]",
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[(truncstorei16 IntRegs:$src, IntRegs:$addr)]>;
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def MOV : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
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"mov $dst, $src", [(set IntRegs:$dst, addr_mode1:$src)]>;
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def MVN : InstARM<(ops IntRegs:$dst, op_addr_mode1:$src),
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"mvn $dst, $src", [(set IntRegs:$dst, (not addr_mode1:$src))]>;
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def ADD : Addr1BinOp<"add", add>;
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def ADCS : Addr1BinOp<"adcs", adde>;
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def ADDS : Addr1BinOp<"adds", addc>;
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def SUB : Addr1BinOp<"sub", sub>;
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def SBCS : Addr1BinOp<"sbcs", sube>;
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def SUBS : Addr1BinOp<"subs", subc>;
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def AND : Addr1BinOp<"and", and>;
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def EOR : Addr1BinOp<"eor", xor>;
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def ORR : Addr1BinOp<"orr", or>;
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let isTwoAddress = 1 in {
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def movcond : InstARM<(ops IntRegs:$dst, IntRegs:$false,
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op_addr_mode1:$true, CCOp:$cc),
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"mov$cc $dst, $true",
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[(set IntRegs:$dst, (armselect addr_mode1:$true,
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IntRegs:$false, imm:$cc))]>;
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def fcpyscond : InstARM<(ops FPRegs:$dst, FPRegs:$false,
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FPRegs:$true, CCOp:$cc),
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"fcpys$cc $dst, $true",
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[(set FPRegs:$dst, (armselect FPRegs:$true,
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FPRegs:$false, imm:$cc))]>;
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def fcpydcond : InstARM<(ops DFPRegs:$dst, DFPRegs:$false,
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DFPRegs:$true, CCOp:$cc),
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"fcpyd$cc $dst, $true",
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[(set DFPRegs:$dst, (armselect DFPRegs:$true,
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DFPRegs:$false, imm:$cc))]>;
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}
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def MUL : IntBinOp<"mul", mul>;
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let Defs = [R0] in {
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def SMULL : IntBinOp<"smull r12,", mulhs>;
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def UMULL : IntBinOp<"umull r12,", mulhu>;
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}
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let isTerminator = 1, isBranch = 1 in {
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def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
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"b$cc $dst",
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[(armbr bb:$dst, imm:$cc)]>;
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def b : InstARM<(ops brtarget:$dst),
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"b $dst",
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[(br bb:$dst)]>;
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}
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def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
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"cmp $a, $b",
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[(armcmp IntRegs:$a, addr_mode1:$b)]>;
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// Floating Point Compare
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def fcmps : InstARM<(ops FPRegs:$a, FPRegs:$b),
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"fcmps $a, $b",
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[(armcmp FPRegs:$a, FPRegs:$b)]>;
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def fcmpd : InstARM<(ops DFPRegs:$a, DFPRegs:$b),
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"fcmpd $a, $b",
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[(armcmp DFPRegs:$a, DFPRegs:$b)]>;
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// Floating Point Copy
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def FCPYS : InstARM<(ops FPRegs:$dst, FPRegs:$src), "fcpys $dst, $src", []>;
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def FCPYD : InstARM<(ops DFPRegs:$dst, DFPRegs:$src), "fcpyd $dst, $src", []>;
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// Floating Point Conversion
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// We use bitconvert for moving the data between the register classes.
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// The format conversion is done with ARM specific nodes
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def FMSR : InstARM<(ops FPRegs:$dst, IntRegs:$src),
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"fmsr $dst, $src", [(set FPRegs:$dst, (bitconvert IntRegs:$src))]>;
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def FMRS : InstARM<(ops IntRegs:$dst, FPRegs:$src),
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"fmrs $dst, $src", [(set IntRegs:$dst, (bitconvert FPRegs:$src))]>;
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def FMRRD : InstARM<(ops IntRegs:$i0, IntRegs:$i1, DFPRegs:$src),
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"fmrrd $i0, $i1, $src", [(armfmrrd IntRegs:$i0, IntRegs:$i1, DFPRegs:$src)]>;
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def FMDRR : InstARM<(ops DFPRegs:$dst, IntRegs:$i0, IntRegs:$i1),
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"fmdrr $dst, $i0, $i1", [(set DFPRegs:$dst, (armfmdrr IntRegs:$i0, IntRegs:$i1))]>;
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def FSITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
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"fsitos $dst, $src", [(set FPRegs:$dst, (armfsitos FPRegs:$src))]>;
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def FTOSIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
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"ftosis $dst, $src", [(set FPRegs:$dst, (armftosis FPRegs:$src))]>;
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def FSITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
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"fsitod $dst, $src", [(set DFPRegs:$dst, (armfsitod FPRegs:$src))]>;
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def FTOSID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
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"ftosid $dst, $src", [(set FPRegs:$dst, (armftosid DFPRegs:$src))]>;
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def FUITOS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
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"fuitos $dst, $src", [(set FPRegs:$dst, (armfuitos FPRegs:$src))]>;
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def FTOUIS : InstARM<(ops FPRegs:$dst, FPRegs:$src),
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"ftouis $dst, $src", [(set FPRegs:$dst, (armftouis FPRegs:$src))]>;
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def FUITOD : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
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"fuitod $dst, $src", [(set DFPRegs:$dst, (armfuitod FPRegs:$src))]>;
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def FTOUID : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
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"ftouid $dst, $src", [(set FPRegs:$dst, (armftouid DFPRegs:$src))]>;
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def FCVTDS : InstARM<(ops DFPRegs:$dst, FPRegs:$src),
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"fcvtds $dst, $src", [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
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def FCVTSD : InstARM<(ops FPRegs:$dst, DFPRegs:$src),
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"fcvtsd $dst, $src", [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
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def FMSTAT : InstARM<(ops ), "fmstat", [(armfmstat)]>;
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// Floating Point Arithmetic
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def FADDS : FPBinOp<"fadds", fadd>;
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def FADDD : DFPBinOp<"faddd", fadd>;
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def FSUBS : FPBinOp<"fsubs", fsub>;
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def FSUBD : DFPBinOp<"fsubd", fsub>;
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def FNEGS : FPUnaryOp<"fnegs", fneg>;
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def FNEGD : DFPUnaryOp<"fnegd", fneg>;
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def FABSS : FPUnaryOp<"fabss", fabs>;
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def FABSD : DFPUnaryOp<"fabsd", fabs>;
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def FMULS : FPBinOp<"fmuls", fmul>;
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def FMULD : DFPBinOp<"fmuld", fmul>;
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def FDIVS : FPBinOp<"fdivs", fdiv>;
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def FDIVD : DFPBinOp<"fdivd", fdiv>;
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// Floating Point Load
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def FLDS : InstARM<(ops FPRegs:$dst, op_addr_mode5:$addr),
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"flds $dst, $addr",
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[(set FPRegs:$dst, (load addr_mode5:$addr))]>;
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def FLDD : InstARM<(ops DFPRegs:$dst, op_addr_mode5:$addr),
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"fldd $dst, $addr",
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[(set DFPRegs:$dst, (load addr_mode5:$addr))]>;
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// Floating Point Store
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def FSTS : InstARM<(ops FPRegs:$src, op_addr_mode5:$addr),
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"fsts $src, $addr",
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[(store FPRegs:$src, addr_mode5:$addr)]>;
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def FSTD : InstARM<(ops DFPRegs:$src, op_addr_mode5:$addr),
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"fstd $src, $addr",
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[(store DFPRegs:$src, addr_mode5:$addr)]>;
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def : Pat<(ARMcall tglobaladdr:$dst),
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(bl tglobaladdr:$dst)>;
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def : Pat<(ARMcall texternalsym:$dst),
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(bl texternalsym:$dst)>;
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def : Pat<(extloadi8 IntRegs:$addr),
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(LDRB IntRegs:$addr)>;
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def : Pat<(extloadi16 IntRegs:$addr),
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(LDRH IntRegs:$addr)>;
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// extload bool -> extload byte
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def : Pat<(extloadi1 IntRegs:$addr), (LDRB IntRegs:$addr)>;
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// zextload bool -> zextload byte
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def : Pat<(i32 (zextloadi1 IntRegs:$addr)), (LDRB IntRegs:$addr)>;
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// truncstore bool -> truncstore byte.
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def : Pat<(truncstorei1 IntRegs:$src, IntRegs:$addr),
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(STRB IntRegs:$src, IntRegs:$addr)>;
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