Benjamin Kramer 1386e9b7b1 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. ... This required light surgery on the assembler and disassembler because the instructions use an uncommon encoding. They are the only two instructions in x86 that use register operands and two immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8		2012-05-29 19:05:25 +00:00
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3DNow.s
2011-09-06-NoNewline.s
address-size.s
intel-syntax-2.s
intel-syntax-encoding.s	Add retw and lretw instructions. Also, fix Intel syntax parsing for all	2012-04-11 01:10:53 +00:00
intel-syntax.s
lit.local.cfg
padlock.s
x86_64-avx-clmul-encoding.s
x86_64-avx-encoding.s	Add support for AVX enhanced comparison predicates. Patch from Kay Tiong Khoo.	2012-04-03 05:20:24 +00:00
x86_64-bmi-encoding.s
x86_64-encoding.s
x86_64-fma3-encoding.s
x86_64-fma4-encoding.s
x86_64-imm-widths.s
x86_64-sse4a.s	Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.	2012-05-29 19:05:25 +00:00
x86_64-xop-encoding.s
x86_directives.s
x86_errors.s
x86_operands.s
x86-32-avx.s
x86-32-coverage.s
x86-32-fma3.s
x86-32.s	Add retw and lretw instructions. Also, fix Intel syntax parsing for all	2012-04-11 01:10:53 +00:00
x86-64.s	Add retw and lretw instructions. Also, fix Intel syntax parsing for all	2012-04-11 01:10:53 +00:00