Andrew Trick 3d74dea4bd Add support for stack map generation in the X86 backend. ... Originally implemented by Lang Hames. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193811 91177308-0d34-0410-b5e6-96231b3b80d8		2013-10-31 22:11:56 +00:00
..
PBQP
Analysis.h
AsmPrinter.h	Produce .weak_def_can_be_hidden for some linkonce_odr values	2013-10-30 22:08:11 +00:00
CalcSpillWeights.h
CallingConvLower.h
CommandFlags.h	Speling fixes.	2013-10-22 15:18:03 +00:00
DAGCombine.h
DFAPacketizer.h
EdgeBundles.h
FastISel.h
FunctionLoweringInfo.h
GCMetadata.h
GCMetadataPrinter.h
GCs.h
GCStrategy.h
IntrinsicLowering.h
ISDOpcodes.h
JITCodeEmitter.h
LatencyPriorityQueue.h
LexicalScopes.h
LinkAllAsmWriterComponents.h
LinkAllCodegenComponents.h
LiveInterval.h	Print register in LiveInterval::print()	2013-10-10 21:29:05 +00:00
LiveIntervalAnalysis.h	Represent RegUnit liveness with LiveRange instance	2013-10-10 21:29:02 +00:00
LiveIntervalUnion.h	Rename LiveRange to LiveInterval::Segment	2013-10-10 21:28:43 +00:00
LiveRangeEdit.h
LiveRegMatrix.h
LiveRegUnits.h	LiveRegUnits: Use *MBB for consistency and convenience.	2013-10-14 22:18:59 +00:00
LiveStackAnalysis.h
LiveVariables.h
MachineBasicBlock.h	Even more spelling fixes for "instruction".	2013-09-28 13:42:22 +00:00
MachineBlockFrequencyInfo.h
MachineBranchProbabilityInfo.h
MachineCodeEmitter.h
MachineCodeInfo.h
MachineConstantPool.h
MachineDominators.h
MachineFrameInfo.h
MachineFunction.h
MachineFunctionAnalysis.h
MachineFunctionPass.h
MachineInstr.h	Rename parameter: defined regs are not incoming.	2013-10-10 21:28:38 +00:00
MachineInstrBuilder.h
MachineInstrBundle.h
MachineJumpTableInfo.h
MachineLoopInfo.h
MachineMemOperand.h
MachineModuleInfo.h
MachineModuleInfoImpls.h
MachineOperand.h
MachinePassRegistry.h
MachinePostDominators.h
MachineRegisterInfo.h
MachineRelocation.h
MachineScheduler.h
MachineSSAUpdater.h
MachineTraceMetrics.h
MachORelocation.h
Passes.h	Simplify formatting and sort these. No functionality changed.	2013-10-15 02:03:44 +00:00
PseudoSourceValue.h
RegAllocPBQP.h
RegAllocRegistry.h
RegisterClassInfo.h
RegisterPressure.h	Represent RegUnit liveness with LiveRange instance	2013-10-10 21:29:02 +00:00
RegisterScavenging.h
ResourcePriorityQueue.h
RuntimeLibcalls.h	LegalizeDAG: allow libcalls for max/min atomic operations	2013-10-25 09:30:20 +00:00
ScheduleDAG.h	Explicitly request unsigned enum types when desired	2013-10-08 20:15:11 +00:00
ScheduleDAGInstrs.h	Even more spelling fixes for "instruction".	2013-09-28 13:42:22 +00:00
ScheduleDFS.h
ScheduleHazardRecognizer.h
SchedulerRegistry.h
ScoreboardHazardRecognizer.h
SelectionDAG.h	Keep TBAA info when rewriting SelectionDAG loads and stores	2013-10-28 11:17:59 +00:00
SelectionDAGISel.h	Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon.	2013-10-05 05:38:16 +00:00
SelectionDAGNodes.h	Remove an old workaround for a compiler that EOL'd years ago.	2013-09-29 19:39:02 +00:00
SlotIndexes.h
StackMaps.h	Add support for stack map generation in the X86 backend.	2013-10-31 22:11:56 +00:00
StackProtector.h	Reformat code with clang-format.	2013-10-30 02:25:14 +00:00
TargetLoweringObjectFileImpl.h
TargetSchedule.h	IfConverter: Use TargetSchedule for instruction latencies	2013-09-30 15:28:56 +00:00
ValueTypes.h	Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).	2013-10-10 17:00:52 +00:00
ValueTypes.td	Implement aarch64 neon instruction set AdvSIMD (Across).	2013-10-05 08:22:10 +00:00
VirtRegMap.h