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4ce42a776a
* Expose information about implicit defs/uses of register through the MachineInstrInfo.h file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4877 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
1.5 KiB
C++
47 lines
1.5 KiB
C++
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
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//
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// This file contains the X86 implementation of the MachineInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "X86InstrInfo.h"
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#include "X86.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES)
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#define IMPREGSLIST(NAME, ...) \
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static const unsigned NAME[] = { __VA_ARGS__ };
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#include "X86InstrInfo.def"
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// X86Insts - Turn the InstrInfo.def file into a bunch of instruction
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// descriptors
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//
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static const MachineInstrDescriptor X86Insts[] = {
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) \
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{ NAME, \
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-1, /* Always vararg */ \
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((TSFLAGS) & X86II::Void) ? -1 : 0, /* Result is in 0 */ \
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0, false, 0, 0, TSFLAGS, FLAGS, TSFLAGS, IMPDEFS, IMPUSES },
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#include "X86InstrInfo.def"
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};
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X86InstrInfo::X86InstrInfo()
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: MachineInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
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}
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static unsigned char BaseOpcodes[] = {
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#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPDEFS, IMPUSES) BASEOPCODE,
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#include "X86InstrInfo.def"
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};
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// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
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// specified opcode number.
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//
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unsigned char X86InstrInfo::getBaseOpcodeFor(unsigned Opcode) const {
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assert(Opcode < sizeof(BaseOpcodes)/sizeof(BaseOpcodes[0]) &&
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"Opcode out of range!");
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return BaseOpcodes[Opcode];
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}
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