llvm-6502/test/CodeGen/Mips/lbu1.ll
Akira Hatanaka 24e79e55da 1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
Change these to patterns.
2. Add another 16 instructions.

Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161272 91177308-0d34-0410-b5e6-96231b3b80d8
2012-08-03 22:57:02 +00:00

20 lines
607 B
LLVM

; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@c = global i8 97, align 1
@.str = private unnamed_addr constant [5 x i8] c"%c \0A\00", align 1
define i32 @main() nounwind {
entry:
%i = alloca i32, align 4
%0 = load i8* @c, align 1
%conv = zext i8 %0 to i32
; 16: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
store i32 %conv, i32* %i, align 4
%1 = load i8* @c, align 1
%conv1 = zext i8 %1 to i32
%call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i32 0, i32 0), i32 %conv1)
ret i32 0
}
declare i32 @printf(i8*, ...)