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https://github.com/c64scene-ar/llvm-6502.git
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cd9ea51986
Use of store or load with the atomic specifier on 64-bit types would cause instruction-selection failures. As with the 32-bit case, these can use the default expansion in terms of cmp-and-swap. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171072 91177308-0d34-0410-b5e6-96231b3b80d8
47 lines
976 B
LLVM
47 lines
976 B
LLVM
; RUN: llc < %s -march=ppc64 | FileCheck %s
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define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
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; CHECK: exchange_and_add:
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; CHECK: ldarx
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%tmp = atomicrmw add i64* %mem, i64 %val monotonic
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define i64 @exchange_and_cmp(i64* %mem) nounwind {
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; CHECK: exchange_and_cmp:
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; CHECK: ldarx
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%tmp = cmpxchg i64* %mem, i64 0, i64 1 monotonic
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; CHECK: stdcx.
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define i64 @exchange(i64* %mem, i64 %val) nounwind {
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; CHECK: exchange:
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; CHECK: ldarx
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%tmp = atomicrmw xchg i64* %mem, i64 1 monotonic
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; CHECK: stdcx.
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ret i64 %tmp
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}
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define void @atomic_store(i64* %mem, i64 %val) nounwind {
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entry:
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; CHECK: @atomic_store
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store atomic i64 %val, i64* %mem release, align 64
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; CHECK: ldarx
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; CHECK: stdcx.
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ret void
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}
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define i64 @atomic_load(i64* %mem) nounwind {
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entry:
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; CHECK: @atomic_load
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%tmp = load atomic i64* %mem acquire, align 64
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; CHECK: ldarx
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; CHECK: stdcx.
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; CHECK: stdcx.
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ret i64 %tmp
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}
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