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https://github.com/c64scene-ar/llvm-6502.git
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82b3821208
The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and unset if it doesn't. The solution up to now was to insert a MachineNode to set/unset the CR bit, which produces a CR vreg. This vreg was then copied into CR bit 6. When the register allocator saw a bunch of these in the same function, it allocated the set/unset CR bit in some random CR register (1 extra instruction) and then emitted CR moves before every vararg function call, rather than just setting and unsetting CR bit 6 directly before every vararg function call. This patch instead inserts a PPCcrset/PPCcrunset instruction which are then matched by a dedicated instruction pattern. Patch by Tobias von Koch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162725 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
1.0 KiB
LLVM
27 lines
1.0 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
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target triple = "powerpc-unknown-linux"
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@.str = private unnamed_addr constant [3 x i8] c"%i\00", align 1
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define void @test(i32 %count) nounwind {
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entry:
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; CHECK: crxor 6, 6, 6
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%call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 1) nounwind
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%cmp2 = icmp sgt i32 %count, 0
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br i1 %cmp2, label %for.body, label %for.end
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for.body: ; preds = %entry, %for.body
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%i.03 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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; CHECK: crxor 6, 6, 6
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%call1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 1) nounwind
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%inc = add nsw i32 %i.03, 1
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%exitcond = icmp eq i32 %inc, %count
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body, %entry
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ret void
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}
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declare i32 @printf(i8* nocapture, ...) nounwind
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