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https://github.com/c64scene-ar/llvm-6502.git
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b453e16855
for a wider range of GOT entries that can hold thread-relative offsets. This matches the behavior of GCC, which was not documented in the PPC64 TLS ABI. The ABI will be updated with the new code sequence. Former sequence: ld 9,x@got@tprel(2) add 9,9,x@tls New sequence: addis 9,2,x@got@tprel@ha ld 9,x@got@tprel@l(9) add 9,9,x@tls Note that a linker optimization exists to transform the new sequence into the shorter sequence when appropriate, by replacing the addis with a nop and modifying the base register and relocation type of the ld. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170209 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
657 B
LLVM
23 lines
657 B
LLVM
; RUN: llc -mcpu=pwr7 -O0 <%s | FileCheck %s
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; Test correct assembly code generation for thread-local storage
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; using the initial-exec model.
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@a = external thread_local global i32
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define signext i32 @main() nounwind {
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entry:
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%retval = alloca i32, align 4
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store i32 0, i32* %retval
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%0 = load i32* @a, align 4
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ret i32 %0
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}
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; CHECK: addis [[REG1:[0-9]+]], 2, a@got@tprel@ha
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; CHECK: ld [[REG2:[0-9]+]], a@got@tprel@l([[REG1]])
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; CHECK: add {{[0-9]+}}, [[REG2]], a@tls
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