Vincent Lejeune cae6801b7d R600: Turn BUILD_VECTOR into Reg_Sequence ...

Reviewed-by: Tom Stellard <thomas.stellard at amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176487 91177308-0d34-0410-b5e6-96231b3b80d8

2013-03-05 15:04:49 +00:00

..

128bit-kernel-args.ll

R600: Add support for 128-bit parameters

2013-02-13 22:05:20 +00:00

add.v4i32.ll

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and.v4i32.ll

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dagcombiner-bug-illegal-vec4-int-to-fp.ll

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disconnected-predset-break-bug.ll

R600: Fix for Unigine when MachineSched is enabled

2013-02-21 15:06:59 +00:00

fabs.ll

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fadd.ll

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fadd.v4f32.ll

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fcmp-cnd.ll

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fcmp-cnde-int-args.ll

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fcmp.ll

R600: Add support for SET*_DX10 instructions

2013-02-07 14:02:35 +00:00

fdiv.v4f32.ll

R600: Turn BUILD_VECTOR into Reg_Sequence

2013-03-05 15:04:49 +00:00

floor.ll

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fmad.ll

R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern

2013-02-18 14:11:28 +00:00

fmax.ll

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fmin.ll

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fmul.ll

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fmul.v4f32.ll

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fsub.ll

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fsub.v4f32.ll

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i8_to_double_to_float.ll

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icmp-select-sete-reverse-args.ll

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kcache-fold.ll

R600: Do not fold single instruction with more that 3 kcache read

2013-02-14 16:57:19 +00:00

lit.local.cfg

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literals.ll

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llvm.AMDGPU.mul.ll

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llvm.AMDGPU.tex.ll

R600: Add lit tests for texture sampling instruction selection.

2013-02-14 07:43:51 +00:00

llvm.AMDGPU.trunc.ll

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llvm.cos.ll

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llvm.pow.ll

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llvm.SI.fs.interp.constant.ll

R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32

2013-02-21 08:57:10 +00:00

llvm.SI.sample.ll

R600/SI: fix sampler tests after fixing wait insertions

2013-03-01 17:39:05 +00:00

llvm.sin.ll

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load.constant_addrspace.f32.ll

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load.i8.ll

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predicates.ll

R600: Add tests for instruction predicates

2013-02-05 17:09:13 +00:00

reciprocal.ll

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sdiv.ll

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selectcc_cnde_int.ll

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selectcc_cnde.ll

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selectcc-icmp-select-float.ll

R600: Fix assembly name for SETGT_INT

2013-02-07 14:02:27 +00:00

set-dx10.ll

R600: Add support for SET*_DX10 instructions

2013-02-07 14:02:35 +00:00

setcc.v4i32.ll

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short-args.ll

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store.v4f32.ll

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store.v4i32.ll

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udiv.v4i32.ll

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unsupported-cc.ll

R600: Add support for SET*_DX10 instructions

2013-02-07 14:02:35 +00:00

urem.v4i32.ll

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vec4-expand.ll

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