mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-26 23:29:22 +00:00
This matches the format produced by the AMD proprietary driver. //==================================================================// // Shell script for converting .ll test cases: (Pass the .ll files you want to convert to this script as arguments). //==================================================================// ; This was necessary on my system so that A-Z in sed would match only ; upper case. I'm not sure why. export LC_ALL='C' TEST_FILES="$*" MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r` for f in $TEST_FILES; do # Check that there are SI tests: grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f if [ $? -eq 0 ]; then for match in $MATCHES; do sed -i -e "s/\([ :]$match\)/\L\1/" $f done # Try to get check lines with partial instruction names sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f fi done sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll //==================================================================// // Shell script for converting .td files (run this last) //==================================================================// export LC_ALL='C' sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
115 lines
4.0 KiB
LLVM
115 lines
4.0 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
|
|
|
|
declare i32 @llvm.bswap.i32(i32) nounwind readnone
|
|
declare <2 x i32> @llvm.bswap.v2i32(<2 x i32>) nounwind readnone
|
|
declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
|
|
declare <8 x i32> @llvm.bswap.v8i32(<8 x i32>) nounwind readnone
|
|
declare i64 @llvm.bswap.i64(i64) nounwind readnone
|
|
declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>) nounwind readnone
|
|
declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) nounwind readnone
|
|
|
|
; FUNC-LABEL: @test_bswap_i32
|
|
; SI: buffer_load_dword [[VAL:v[0-9]+]]
|
|
; SI-DAG: v_alignbit_b32 [[TMP0:v[0-9]+]], [[VAL]], [[VAL]], 8
|
|
; SI-DAG: v_alignbit_b32 [[TMP1:v[0-9]+]], [[VAL]], [[VAL]], 24
|
|
; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0xff00ff
|
|
; SI: v_bfi_b32 [[RESULT:v[0-9]+]], [[K]], [[TMP1]], [[TMP0]]
|
|
; SI: buffer_store_dword [[RESULT]]
|
|
; SI: s_endpgm
|
|
define void @test_bswap_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
|
|
%val = load i32 addrspace(1)* %in, align 4
|
|
%bswap = call i32 @llvm.bswap.i32(i32 %val) nounwind readnone
|
|
store i32 %bswap, i32 addrspace(1)* %out, align 4
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: @test_bswap_v2i32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI: s_endpgm
|
|
define void @test_bswap_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind {
|
|
%val = load <2 x i32> addrspace(1)* %in, align 8
|
|
%bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %val) nounwind readnone
|
|
store <2 x i32> %bswap, <2 x i32> addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: @test_bswap_v4i32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI: s_endpgm
|
|
define void @test_bswap_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) nounwind {
|
|
%val = load <4 x i32> addrspace(1)* %in, align 16
|
|
%bswap = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %val) nounwind readnone
|
|
store <4 x i32> %bswap, <4 x i32> addrspace(1)* %out, align 16
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: @test_bswap_v8i32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_alignbit_b32
|
|
; SI-DAG: v_bfi_b32
|
|
; SI: s_endpgm
|
|
define void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) nounwind {
|
|
%val = load <8 x i32> addrspace(1)* %in, align 32
|
|
%bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone
|
|
store <8 x i32> %bswap, <8 x i32> addrspace(1)* %out, align 32
|
|
ret void
|
|
}
|
|
|
|
define void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
|
|
%val = load i64 addrspace(1)* %in, align 8
|
|
%bswap = call i64 @llvm.bswap.i64(i64 %val) nounwind readnone
|
|
store i64 %bswap, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind {
|
|
%val = load <2 x i64> addrspace(1)* %in, align 16
|
|
%bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %val) nounwind readnone
|
|
store <2 x i64> %bswap, <2 x i64> addrspace(1)* %out, align 16
|
|
ret void
|
|
}
|
|
|
|
define void @test_bswap_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) nounwind {
|
|
%val = load <4 x i64> addrspace(1)* %in, align 32
|
|
%bswap = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %val) nounwind readnone
|
|
store <4 x i64> %bswap, <4 x i64> addrspace(1)* %out, align 32
|
|
ret void
|
|
}
|