Matt Fleming d8a33ddcfe Currently, createMachOStreamer() is invoked directly in llvm-mc which ... isn't ideal if we want to be able to use another object file format. Add a createObjectStreamer() factory method so that the correct object file streamer can be instantiated for a given target triple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104318 91177308-0d34-0410-b5e6-96231b3b80d8		2010-05-21 12:54:43 +00:00
..
Mangler.h	give Mangler access to TargetData.	2010-03-12 20:47:28 +00:00
SubtargetFeature.h	The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a	2010-05-11 00:30:02 +00:00
Target.td	tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor	2010-05-20 20:20:32 +00:00
TargetAsmBackend.h	MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can	2010-05-12 00:38:17 +00:00
TargetAsmLexer.h
TargetAsmParser.h
TargetCallingConv.td
TargetData.h
TargetELFWriterInfo.h
TargetFrameInfo.h
TargetInstrDesc.h	add a convenient TargetInstrDesc::getNumImplicitUses/Defs method.	2010-03-24 23:07:47 +00:00
TargetInstrInfo.h	Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it	2010-05-06 20:33:48 +00:00
TargetInstrItineraries.h	Initial support for different kinds of FU reservation.	2010-04-07 18:19:32 +00:00
TargetIntrinsicInfo.h
TargetJITInfo.h
TargetLowering.h	Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.	2010-05-20 23:26:43 +00:00
TargetLoweringObjectFile.h	fix a fixme in TargetLoweringObjectFile::getExprForDwarfReference	2010-03-11 21:55:20 +00:00
TargetMachine.h	Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.	2010-05-20 23:26:43 +00:00
TargetOpcodes.h	Add a pseudo instruction REG_SEQUENCE that takes a list of registers and	2010-05-01 00:28:44 +00:00
TargetOptions.h	Remove the -enable-sjlj-eh option, which doesn't do anything.	2010-05-02 15:36:26 +00:00
TargetRegisterInfo.h	Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE	2010-05-14 23:21:14 +00:00
TargetRegistry.h	Currently, createMachOStreamer() is invoked directly in llvm-mc which	2010-05-21 12:54:43 +00:00
TargetSchedule.td	Make processor FUs unique for given itinerary. This extends the limit of 32	2010-04-18 20:31:01 +00:00
TargetSelect.h
TargetSelectionDAG.td	finally remove the immAllOnesV_bc/immAllZerosV_bc patterns	2010-03-28 08:43:23 +00:00
TargetSelectionDAGInfo.h	Fix a comment.	2010-05-11 18:03:41 +00:00
TargetSubtarget.h