Pete Cooper d90099d36c Clear kill flags on all used registers when sinking instructions. ...

The test here was sinking the AND here to a lower BB:

	%vreg7<def> = ANDWri %vreg8, 0; GPR32common:%vreg7,%vreg8
	TBNZW %vreg8<kill>, 0, <BB#1>; GPR32common:%vreg8

which meant that vreg8 was read after it was killed.

This commit changes the code from clearing kill flags on the AND to clearing flags on all registers used by the AND.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236886 91177308-0d34-0410-b5e6-96231b3b80d8

2015-05-08 17:54:32 +00:00

..

AArch64

Clear kill flags on all used registers when sinking instructions.

2015-05-08 17:54:32 +00:00

ARM

Clear kill flags in tail duplication.

2015-05-07 21:48:26 +00:00

BPF

…

CPP

…

Generic

[Hexagon] r236351 fix does not work on builder configurations yet.

2015-05-01 22:39:20 +00:00

Hexagon

[Hexagon] Update AnalyzeBranch, etc target hooks

2015-05-08 16:16:29 +00:00

Inputs

IR: Give 'DI' prefix to debug info metadata

2015-04-29 16:38:44 +00:00

Mips

[mips] Emit the .insn directive for empty basic blocks.

2015-05-08 09:10:15 +00:00

MSP430

…

NVPTX

[NVPTX] Handle addrspacecast constant expressions in aggregate initializers

2015-04-28 17:18:30 +00:00

PowerPC

Fix test added in r236850 for OSX builders.

2015-05-08 14:04:54 +00:00

R600

R600/SI: Add VCC as an implict def of SI_KILL

2015-05-01 03:44:09 +00:00

SPARC

…

SystemZ

[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load

2015-05-05 19:34:10 +00:00

Thumb

IR: Give 'DI' prefix to debug info metadata

2015-04-29 16:38:44 +00:00

Thumb2

Thumb2SizeReduction: Check the correct set of registers for LDMIA.

2015-05-05 20:07:10 +00:00

WinEH

Flip r236172 testcase RUN option ordering for BSD sed(1). NFC.

2015-04-30 00:07:34 +00:00

X86

[X86] Teach 'getTargetShuffleMask' how to look through ISD::WrapperRIP when decoding a PSHUFB mask.

2015-05-08 15:11:07 +00:00

XCore

IR: Give 'DI' prefix to debug info metadata

2015-04-29 16:38:44 +00:00