Pete Cooper d90099d36c Clear kill flags on all used registers when sinking instructions. ... The test here was sinking the AND here to a lower BB: %vreg7<def> = ANDWri %vreg8, 0; GPR32common:%vreg7,%vreg8 TBNZW %vreg8<kill>, 0, <BB#1>; GPR32common:%vreg8 which meant that vreg8 was read after it was killed. This commit changes the code from clearing kill flags on the AND to clearing flags on all registers used by the AND. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236886 91177308-0d34-0410-b5e6-96231b3b80d8		2015-05-08 17:54:32 +00:00
..
AArch64	Clear kill flags on all used registers when sinking instructions.	2015-05-08 17:54:32 +00:00
ARM	Clear kill flags in tail duplication.	2015-05-07 21:48:26 +00:00
BPF
CPP
Generic
Hexagon	[Hexagon] Update AnalyzeBranch, etc target hooks	2015-05-08 16:16:29 +00:00
Inputs
Mips	[mips] Emit the .insn directive for empty basic blocks.	2015-05-08 09:10:15 +00:00
MSP430
NVPTX
PowerPC	Fix test added in r236850 for OSX builders.	2015-05-08 14:04:54 +00:00
R600
SPARC
SystemZ	[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load	2015-05-05 19:34:10 +00:00
Thumb
Thumb2	Thumb2SizeReduction: Check the correct set of registers for LDMIA.	2015-05-05 20:07:10 +00:00
WinEH
X86	[X86] Teach 'getTargetShuffleMask' how to look through ISD::WrapperRIP when decoding a PSHUFB mask.	2015-05-08 15:11:07 +00:00
XCore