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https://github.com/c64scene-ar/llvm-6502.git
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e56023a059
Finish off PR23080 by renaming the debug info IR constructs from `MD*` to `DI*`. The last of the `DIDescriptor` classes were deleted in r235356, and the last of the related typedefs removed in r235413, so this has all baked for about a week. Note: If you have out-of-tree code (like a frontend), I recommend that you get everything compiling and tests passing with the *previous* commit before updating to this one. It'll be easier to keep track of what code is using the `DIDescriptor` hierarchy and what you've already updated, and I think you're extremely unlikely to insert bugs. YMMV of course. Back to *this* commit: I did this using the rename-md-di-nodes.sh upgrade script I've attached to PR23080 (both code and testcases) and filtered through clang-format-diff.py. I edited the tests for test/Assembler/invalid-generic-debug-node-*.ll by hand since the columns were off-by-three. It should work on your out-of-tree testcases (and code, if you've followed the advice in the previous paragraph). Some of the tests are in badly named files now (e.g., test/Assembler/invalid-mdcompositetype-missing-tag.ll should be 'dicompositetype'); I'll come back and move the files in a follow-up commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236120 91177308-0d34-0410-b5e6-96231b3b80d8
557 lines
20 KiB
C++
557 lines
20 KiB
C++
//===-- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a printer that converts from our internal representation
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// of machine-dependent LLVM code to the AArch64 assembly language.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "AArch64.h"
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#include "AArch64MCInstLower.h"
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#include "AArch64MachineFunctionInfo.h"
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#include "AArch64RegisterInfo.h"
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#include "AArch64Subtarget.h"
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#include "InstPrinter/AArch64InstPrinter.h"
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#include "MCTargetDesc/AArch64MCExpr.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/CodeGen/StackMaps.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/IR/DebugInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCLinkerOptimizationHint.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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namespace {
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class AArch64AsmPrinter : public AsmPrinter {
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AArch64MCInstLower MCInstLowering;
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StackMaps SM;
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public:
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AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
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: AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
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SM(*this), AArch64FI(nullptr) {}
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const char *getPassName() const override {
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return "AArch64 Assembly Printer";
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}
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/// \brief Wrapper for MCInstLowering.lowerOperand() for the
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/// tblgen'erated pseudo lowering.
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bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
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return MCInstLowering.lowerOperand(MO, MCOp);
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}
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void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
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const MachineInstr &MI);
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void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
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const MachineInstr &MI);
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/// \brief tblgen'erated driver function for lowering simple MI->MC
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/// pseudo instructions.
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bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
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const MachineInstr *MI);
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void EmitInstruction(const MachineInstr *MI) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AsmPrinter::getAnalysisUsage(AU);
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AU.setPreservesAll();
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}
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bool runOnMachineFunction(MachineFunction &F) override {
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AArch64FI = F.getInfo<AArch64FunctionInfo>();
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return AsmPrinter::runOnMachineFunction(F);
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}
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private:
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MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
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void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
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bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
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bool printAsmRegInClass(const MachineOperand &MO,
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const TargetRegisterClass *RC, bool isVector,
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raw_ostream &O);
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O) override;
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &O) override;
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void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
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void EmitFunctionBodyEnd() override;
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MCSymbol *GetCPISymbol(unsigned CPID) const override;
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void EmitEndOfAsmFile(Module &M) override;
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AArch64FunctionInfo *AArch64FI;
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/// \brief Emit the LOHs contained in AArch64FI.
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void EmitLOHs();
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typedef std::map<const MachineInstr *, MCSymbol *> MInstToMCSymbol;
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MInstToMCSymbol LOHInstToLabel;
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};
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} // end of anonymous namespace
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//===----------------------------------------------------------------------===//
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void AArch64AsmPrinter::EmitEndOfAsmFile(Module &M) {
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Triple TT(TM.getTargetTriple());
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if (TT.isOSBinFormatMachO()) {
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// Funny Darwin hack: This flag tells the linker that no global symbols
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// contain code that falls through to other global symbols (e.g. the obvious
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// implementation of multiple entry points). If this doesn't occur, the
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// linker can safely perform dead code stripping. Since LLVM never
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// generates code that does this, it is always safe to set.
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OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
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SM.serializeToStackMapSection();
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}
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}
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MachineLocation
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AArch64AsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
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MachineLocation Location;
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assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
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// Frame address. Currently handles register +- offset only.
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if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
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Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
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else {
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DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
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}
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return Location;
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}
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void AArch64AsmPrinter::EmitLOHs() {
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SmallVector<MCSymbol *, 3> MCArgs;
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for (const auto &D : AArch64FI->getLOHContainer()) {
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for (const MachineInstr *MI : D.getArgs()) {
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MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI);
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assert(LabelIt != LOHInstToLabel.end() &&
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"Label hasn't been inserted for LOH related instruction");
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MCArgs.push_back(LabelIt->second);
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}
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OutStreamer->EmitLOHDirective(D.getKind(), MCArgs);
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MCArgs.clear();
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}
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}
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void AArch64AsmPrinter::EmitFunctionBodyEnd() {
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if (!AArch64FI->getLOHRelated().empty())
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EmitLOHs();
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}
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/// GetCPISymbol - Return the symbol for the specified constant pool entry.
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MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const {
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// Darwin uses a linker-private symbol name for constant-pools (to
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// avoid addends on the relocation?), ELF has no such concept and
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// uses a normal private symbol.
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if (getDataLayout().getLinkerPrivateGlobalPrefix()[0])
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return OutContext.GetOrCreateSymbol(
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Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
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Twine(getFunctionNumber()) + "_" + Twine(CPID));
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return OutContext.GetOrCreateSymbol(
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Twine(getDataLayout().getPrivateGlobalPrefix()) + "CPI" +
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Twine(getFunctionNumber()) + "_" + Twine(CPID));
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}
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void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
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raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(OpNum);
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switch (MO.getType()) {
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default:
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llvm_unreachable("<unknown operand type>");
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case MachineOperand::MO_Register: {
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unsigned Reg = MO.getReg();
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assert(TargetRegisterInfo::isPhysicalRegister(Reg));
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assert(!MO.getSubReg() && "Subregs should be eliminated!");
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O << AArch64InstPrinter::getRegisterName(Reg);
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break;
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}
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case MachineOperand::MO_Immediate: {
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int64_t Imm = MO.getImm();
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O << '#' << Imm;
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break;
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}
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case MachineOperand::MO_GlobalAddress: {
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const GlobalValue *GV = MO.getGlobal();
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MCSymbol *Sym = getSymbol(GV);
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// FIXME: Can we get anything other than a plain symbol here?
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assert(!MO.getTargetFlags() && "Unknown operand target flag!");
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O << *Sym;
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printOffset(MO.getOffset(), O);
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break;
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}
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}
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}
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bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
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raw_ostream &O) {
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unsigned Reg = MO.getReg();
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switch (Mode) {
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default:
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return true; // Unknown mode.
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case 'w':
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Reg = getWRegFromXReg(Reg);
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break;
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case 'x':
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Reg = getXRegFromWReg(Reg);
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break;
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}
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O << AArch64InstPrinter::getRegisterName(Reg);
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return false;
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}
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// Prints the register in MO using class RC using the offset in the
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// new register class. This should not be used for cross class
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// printing.
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bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
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const TargetRegisterClass *RC,
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bool isVector, raw_ostream &O) {
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assert(MO.isReg() && "Should only get here with a register!");
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const AArch64RegisterInfo *RI =
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MF->getSubtarget<AArch64Subtarget>().getRegisterInfo();
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unsigned Reg = MO.getReg();
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unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
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assert(RI->regsOverlap(RegToPrint, Reg));
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O << AArch64InstPrinter::getRegisterName(
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RegToPrint, isVector ? AArch64::vreg : AArch64::NoRegAltName);
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return false;
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}
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bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
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unsigned AsmVariant,
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const char *ExtraCode, raw_ostream &O) {
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const MachineOperand &MO = MI->getOperand(OpNum);
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// First try the generic code, which knows about modifiers like 'c' and 'n'.
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if (!AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O))
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return false;
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// Does this asm operand have a single letter operand modifier?
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if (ExtraCode && ExtraCode[0]) {
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if (ExtraCode[1] != 0)
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return true; // Unknown modifier.
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switch (ExtraCode[0]) {
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default:
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return true; // Unknown modifier.
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case 'w': // Print W register
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case 'x': // Print X register
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if (MO.isReg())
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return printAsmMRegister(MO, ExtraCode[0], O);
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if (MO.isImm() && MO.getImm() == 0) {
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unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
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O << AArch64InstPrinter::getRegisterName(Reg);
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return false;
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}
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printOperand(MI, OpNum, O);
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return false;
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case 'b': // Print B register.
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case 'h': // Print H register.
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case 's': // Print S register.
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case 'd': // Print D register.
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case 'q': // Print Q register.
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if (MO.isReg()) {
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const TargetRegisterClass *RC;
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switch (ExtraCode[0]) {
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case 'b':
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RC = &AArch64::FPR8RegClass;
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break;
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case 'h':
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RC = &AArch64::FPR16RegClass;
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break;
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case 's':
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RC = &AArch64::FPR32RegClass;
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break;
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case 'd':
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RC = &AArch64::FPR64RegClass;
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break;
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case 'q':
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RC = &AArch64::FPR128RegClass;
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break;
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default:
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return true;
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}
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return printAsmRegInClass(MO, RC, false /* vector */, O);
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}
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printOperand(MI, OpNum, O);
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return false;
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}
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}
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// According to ARM, we should emit x and v registers unless we have a
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// modifier.
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if (MO.isReg()) {
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unsigned Reg = MO.getReg();
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// If this is a w or x register, print an x register.
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if (AArch64::GPR32allRegClass.contains(Reg) ||
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AArch64::GPR64allRegClass.contains(Reg))
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return printAsmMRegister(MO, 'x', O);
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// If this is a b, h, s, d, or q register, print it as a v register.
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return printAsmRegInClass(MO, &AArch64::FPR128RegClass, true /* vector */,
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O);
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}
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printOperand(MI, OpNum, O);
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return false;
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}
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bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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unsigned OpNum,
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unsigned AsmVariant,
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const char *ExtraCode,
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raw_ostream &O) {
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if (ExtraCode && ExtraCode[0])
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return true; // Unknown modifier.
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const MachineOperand &MO = MI->getOperand(OpNum);
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assert(MO.isReg() && "unexpected inline asm memory operand");
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O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]";
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return false;
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}
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void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
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raw_ostream &OS) {
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unsigned NOps = MI->getNumOperands();
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assert(NOps == 4);
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OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
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// cast away const; DIetc do not take const operands for some reason.
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OS << cast<DILocalVariable>(MI->getOperand(NOps - 2).getMetadata())
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->getName();
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OS << " <- ";
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// Frame address. Currently handles register +- offset only.
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assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
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OS << '[';
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printOperand(MI, 0, OS);
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OS << '+';
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printOperand(MI, 1, OS);
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OS << ']';
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OS << "+";
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printOperand(MI, NOps - 2, OS);
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}
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void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
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const MachineInstr &MI) {
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unsigned NumNOPBytes = MI.getOperand(1).getImm();
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SM.recordStackMap(MI);
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assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
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// Scan ahead to trim the shadow.
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const MachineBasicBlock &MBB = *MI.getParent();
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MachineBasicBlock::const_iterator MII(MI);
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++MII;
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while (NumNOPBytes > 0) {
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if (MII == MBB.end() || MII->isCall() ||
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MII->getOpcode() == AArch64::DBG_VALUE ||
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MII->getOpcode() == TargetOpcode::PATCHPOINT ||
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MII->getOpcode() == TargetOpcode::STACKMAP)
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break;
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++MII;
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NumNOPBytes -= 4;
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}
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// Emit nops.
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for (unsigned i = 0; i < NumNOPBytes; i += 4)
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EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
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}
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// Lower a patchpoint of the form:
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// [<def>], <id>, <numBytes>, <target>, <numArgs>
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void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
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const MachineInstr &MI) {
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SM.recordPatchPoint(MI);
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PatchPointOpers Opers(&MI);
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int64_t CallTarget = Opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
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unsigned EncodedBytes = 0;
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if (CallTarget) {
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assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
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"High 16 bits of call target should be zero.");
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unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
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EncodedBytes = 16;
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// Materialize the jump address:
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EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZWi)
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.addReg(ScratchReg)
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.addImm((CallTarget >> 32) & 0xFFFF)
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.addImm(32));
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EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKWi)
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.addReg(ScratchReg)
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.addReg(ScratchReg)
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.addImm((CallTarget >> 16) & 0xFFFF)
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.addImm(16));
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EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKWi)
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.addReg(ScratchReg)
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.addReg(ScratchReg)
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.addImm(CallTarget & 0xFFFF)
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.addImm(0));
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EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
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}
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// Emit padding.
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unsigned NumBytes = Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
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assert(NumBytes >= EncodedBytes &&
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"Patchpoint can't request size less than the length of a call.");
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assert((NumBytes - EncodedBytes) % 4 == 0 &&
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"Invalid number of NOP bytes requested!");
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for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
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EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
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}
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// Simple pseudo-instructions have their lowering (with expansion to real
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// instructions) auto-generated.
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#include "AArch64GenMCPseudoLowering.inc"
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void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
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// Do any auto-generated pseudo lowerings.
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if (emitPseudoExpansionLowering(*OutStreamer, MI))
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return;
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if (AArch64FI->getLOHRelated().count(MI)) {
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// Generate a label for LOH related instruction
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MCSymbol *LOHLabel = createTempSymbol("loh");
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// Associate the instruction with the label
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LOHInstToLabel[MI] = LOHLabel;
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OutStreamer->EmitLabel(LOHLabel);
|
|
}
|
|
|
|
// Do any manual lowerings.
|
|
switch (MI->getOpcode()) {
|
|
default:
|
|
break;
|
|
case AArch64::DBG_VALUE: {
|
|
if (isVerbose() && OutStreamer->hasRawTextSupport()) {
|
|
SmallString<128> TmpStr;
|
|
raw_svector_ostream OS(TmpStr);
|
|
PrintDebugValueComment(MI, OS);
|
|
OutStreamer->EmitRawText(StringRef(OS.str()));
|
|
}
|
|
return;
|
|
}
|
|
|
|
// Tail calls use pseudo instructions so they have the proper code-gen
|
|
// attributes (isCall, isReturn, etc.). We lower them to the real
|
|
// instruction here.
|
|
case AArch64::TCRETURNri: {
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(AArch64::BR);
|
|
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
|
EmitToStreamer(*OutStreamer, TmpInst);
|
|
return;
|
|
}
|
|
case AArch64::TCRETURNdi: {
|
|
MCOperand Dest;
|
|
MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
|
|
MCInst TmpInst;
|
|
TmpInst.setOpcode(AArch64::B);
|
|
TmpInst.addOperand(Dest);
|
|
EmitToStreamer(*OutStreamer, TmpInst);
|
|
return;
|
|
}
|
|
case AArch64::TLSDESC_CALLSEQ: {
|
|
/// lower this to:
|
|
/// adrp x0, :tlsdesc:var
|
|
/// ldr x1, [x0, #:tlsdesc_lo12:var]
|
|
/// add x0, x0, #:tlsdesc_lo12:var
|
|
/// .tlsdesccall var
|
|
/// blr x1
|
|
/// (TPIDR_EL0 offset now in x0)
|
|
const MachineOperand &MO_Sym = MI->getOperand(0);
|
|
MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
|
|
MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
|
|
MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF |
|
|
AArch64II::MO_NC);
|
|
MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
|
|
MCInstLowering.lowerOperand(MO_Sym, Sym);
|
|
MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
|
|
MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
|
|
|
|
MCInst Adrp;
|
|
Adrp.setOpcode(AArch64::ADRP);
|
|
Adrp.addOperand(MCOperand::CreateReg(AArch64::X0));
|
|
Adrp.addOperand(SymTLSDesc);
|
|
EmitToStreamer(*OutStreamer, Adrp);
|
|
|
|
MCInst Ldr;
|
|
Ldr.setOpcode(AArch64::LDRXui);
|
|
Ldr.addOperand(MCOperand::CreateReg(AArch64::X1));
|
|
Ldr.addOperand(MCOperand::CreateReg(AArch64::X0));
|
|
Ldr.addOperand(SymTLSDescLo12);
|
|
Ldr.addOperand(MCOperand::CreateImm(0));
|
|
EmitToStreamer(*OutStreamer, Ldr);
|
|
|
|
MCInst Add;
|
|
Add.setOpcode(AArch64::ADDXri);
|
|
Add.addOperand(MCOperand::CreateReg(AArch64::X0));
|
|
Add.addOperand(MCOperand::CreateReg(AArch64::X0));
|
|
Add.addOperand(SymTLSDescLo12);
|
|
Add.addOperand(MCOperand::CreateImm(AArch64_AM::getShiftValue(0)));
|
|
EmitToStreamer(*OutStreamer, Add);
|
|
|
|
// Emit a relocation-annotation. This expands to no code, but requests
|
|
// the following instruction gets an R_AARCH64_TLSDESC_CALL.
|
|
MCInst TLSDescCall;
|
|
TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
|
|
TLSDescCall.addOperand(Sym);
|
|
EmitToStreamer(*OutStreamer, TLSDescCall);
|
|
|
|
MCInst Blr;
|
|
Blr.setOpcode(AArch64::BLR);
|
|
Blr.addOperand(MCOperand::CreateReg(AArch64::X1));
|
|
EmitToStreamer(*OutStreamer, Blr);
|
|
|
|
return;
|
|
}
|
|
|
|
case TargetOpcode::STACKMAP:
|
|
return LowerSTACKMAP(*OutStreamer, SM, *MI);
|
|
|
|
case TargetOpcode::PATCHPOINT:
|
|
return LowerPATCHPOINT(*OutStreamer, SM, *MI);
|
|
}
|
|
|
|
// Finally, do the automated lowerings for everything else.
|
|
MCInst TmpInst;
|
|
MCInstLowering.Lower(MI, TmpInst);
|
|
EmitToStreamer(*OutStreamer, TmpInst);
|
|
}
|
|
|
|
// Force static initialization.
|
|
extern "C" void LLVMInitializeAArch64AsmPrinter() {
|
|
RegisterAsmPrinter<AArch64AsmPrinter> X(TheAArch64leTarget);
|
|
RegisterAsmPrinter<AArch64AsmPrinter> Y(TheAArch64beTarget);
|
|
RegisterAsmPrinter<AArch64AsmPrinter> Z(TheARM64Target);
|
|
}
|