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https://github.com/c64scene-ar/llvm-6502.git
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34ad085eec
Summary: Expand list of supported targets for Mips to include mips32 r1. Previously it only include r2. More patches are coming where there is a difference but in the current patches as pushed upstream, r1 and r2 are equivalent. Test Plan: simplestorefp1.ll add new build bots at mips to test this flavor at both -O0 and -O2 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5306 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217821 91177308-0d34-0410-b5e6-96231b3b80d8
86 lines
2.3 KiB
LLVM
86 lines
2.3 KiB
LLVM
; ModuleID = 'loadstore2.c'
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target datalayout = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
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target triple = "mips--linux-gnu"
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@c2 = common global i8 0, align 1
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@c1 = common global i8 0, align 1
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
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; RUN: < %s | FileCheck %s
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
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; RUN: < %s | FileCheck %s
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@s2 = common global i16 0, align 2
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@s1 = common global i16 0, align 2
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@i2 = common global i32 0, align 4
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@i1 = common global i32 0, align 4
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@f2 = common global float 0.000000e+00, align 4
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@f1 = common global float 0.000000e+00, align 4
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@d2 = common global double 0.000000e+00, align 8
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@d1 = common global double 0.000000e+00, align 8
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; Function Attrs: nounwind
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define void @cfoo() #0 {
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entry:
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%0 = load i8* @c2, align 1
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store i8 %0, i8* @c1, align 1
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; CHECK-LABEL: cfoo:
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; CHECK: lbu $[[REGc:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: sb $[[REGc]], 0(${{[0-9]+}})
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ret void
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}
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; Function Attrs: nounwind
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define void @sfoo() #0 {
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entry:
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%0 = load i16* @s2, align 2
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store i16 %0, i16* @s1, align 2
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; CHECK-LABEL: sfoo:
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; CHECK: lhu $[[REGs:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: sh $[[REGs]], 0(${{[0-9]+}})
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ret void
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}
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; Function Attrs: nounwind
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define void @ifoo() #0 {
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entry:
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%0 = load i32* @i2, align 4
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store i32 %0, i32* @i1, align 4
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; CHECK-LABEL: ifoo:
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; CHECK: lw $[[REGi:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: sw $[[REGi]], 0(${{[0-9]+}})
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ret void
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}
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; Function Attrs: nounwind
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define void @ffoo() #0 {
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entry:
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%0 = load float* @f2, align 4
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store float %0, float* @f1, align 4
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; CHECK-LABEL: ffoo:
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; CHECK: lwc1 $f[[REGf:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: swc1 $f[[REGf]], 0(${{[0-9]+}})
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ret void
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}
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; Function Attrs: nounwind
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define void @dfoo() #0 {
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entry:
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%0 = load double* @d2, align 8
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store double %0, double* @d1, align 8
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; CHECK-LABEL: dfoo:
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; CHECK: ldc1 $f[[REGd:[0-9]+]], 0(${{[0-9]+}})
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; CHECK: sdc1 $f[[REGd]], 0(${{[0-9]+}})
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; CHECK: .end dfoo
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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