Arnold Schwaighofer b4b7a52ec5 Change swift/vldm test case to be less dependent on allocation order ... 'Force' values in registers using the calling convention. Now, we only depend on the calling convention and that the allocator performs copy coalescing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189985 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-04 20:51:06 +00:00
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AArch64	Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:	2013-09-04 09:28:24 +00:00
ARM	Change swift/vldm test case to be less dependent on allocation order	2013-09-04 20:51:06 +00:00
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Mips	Make sure we don't generate stubs for any of these functions because they	2013-09-01 04:12:59 +00:00
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PowerPC	[PowerPC] Call support for fast-isel.	2013-08-30 22:18:55 +00:00
R600	R600: Use shared op optimization when checking cycle compatibility	2013-09-04 19:53:54 +00:00
SPARC	[Sparc] Fix an assertion failure while lowering fcmp on long double.	2013-09-04 15:15:20 +00:00
SystemZ	[SystemZ] Add support for TMHH, TMHL, TMLH and TMLL	2013-09-03 15:38:35 +00:00
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X86	FileCheck-ize three tests of llvm/test/CodeGen/X86/h-register(s).	2013-09-02 12:00:53 +00:00
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