llvm-6502/lib
Akira Hatanaka db8e0bbedb [mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-01 20:31:44 +00:00
..
Analysis
AsmParser
Bitcode
CodeGen
DebugInfo
ExecutionEngine
IR
IRReader
Linker
MC
Object
Option
Support
TableGen
Target [mips] Increase the number of floating point control registers available to 32. 2013-07-01 20:31:44 +00:00
Transforms
CMakeLists.txt
LLVMBuild.txt
Makefile