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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
22 lines
645 B
LLVM
22 lines
645 B
LLVM
; RUN: llc < %s -O0 -mtriple=armv4t--linux-eabi-android
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; RUN: llc < %s -O0 -mtriple=armv4t-unknown-linux
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; RUN: llc < %s -O0 -mtriple=armv5-unknown-linux
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; See http://llvm.org/bugs/show_bug.cgi?id=16178
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; ARMFastISel used to fail emitting sext/zext in pre-ARMv6.
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; Function Attrs: nounwind
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define arm_aapcscc void @f2(i8 signext %a) #0 {
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entry:
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%a.addr = alloca i8, align 1
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store i8 %a, i8* %a.addr, align 1
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%0 = load i8, i8* %a.addr, align 1
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%conv = sext i8 %0 to i32
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%shr = ashr i32 %conv, 56
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%conv1 = trunc i32 %shr to i8
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call arm_aapcscc void @f1(i8 signext %conv1)
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ret void
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}
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declare arm_aapcscc void @f1(i8 signext) #1
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