mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 15:11:24 +00:00
7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
332 lines
7.0 KiB
LLVM
332 lines
7.0 KiB
LLVM
; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM
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; RUN: llc < %s -mtriple=thumb-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2
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; rdar://8662825
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define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
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; ARM-LABEL: t1:
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; ARM: suble r1, r1, #-2147483647
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; ARM: mov r0, r1
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; T2-LABEL: t1:
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; T2: mvn r0, #-2147483648
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; T2: addle r1, r0
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; T2: mov r0, r1
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 2147483647
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%tmp3 = add i32 %tmp2, %b
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ret i32 %tmp3
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}
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define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; ARM-LABEL: t2:
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; ARM: suble r1, r1, #10
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; ARM: mov r0, r1
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; T2-LABEL: t2:
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; T2: suble r1, #10
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; T2: mov r0, r1
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%tmp1 = icmp sgt i32 %c, 10
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%tmp2 = select i1 %tmp1, i32 0, i32 10
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%tmp3 = sub i32 %b, %tmp2
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ret i32 %tmp3
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}
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define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
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; ARM-LABEL: t3:
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; ARM: andge r3, r3, r2
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; ARM: mov r0, r3
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; T2-LABEL: t3:
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; T2: andge r3, r2
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; T2: mov r0, r3
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%cond = icmp slt i32 %a, %b
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%z = select i1 %cond, i32 -1, i32 %x
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%s = and i32 %z, %y
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ret i32 %s
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}
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define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
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; ARM-LABEL: t4:
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; ARM: orrge r3, r3, r2
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; ARM: mov r0, r3
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; T2-LABEL: t4:
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; T2: orrge r3, r2
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; T2: mov r0, r3
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%cond = icmp slt i32 %a, %b
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%z = select i1 %cond, i32 0, i32 %x
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%s = or i32 %z, %y
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ret i32 %s
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}
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define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
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entry:
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; ARM-LABEL: t5:
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; ARM-NOT: moveq
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; ARM: orreq r2, r2, #1
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; T2-LABEL: t5:
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; T2-NOT: moveq
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; T2: orreq r2, r2, #1
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%tmp1 = icmp eq i32 %a, %b
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%tmp2 = zext i1 %tmp1 to i32
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%tmp3 = or i32 %tmp2, %c
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ret i32 %tmp3
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}
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define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; ARM-LABEL: t6:
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; ARM-NOT: movge
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; ARM: eorlt r3, r3, r2
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; T2-LABEL: t6:
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; T2-NOT: movge
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; T2: eorlt r3, r2
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %c, i32 0
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%tmp2 = xor i32 %tmp1, %d
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ret i32 %tmp2
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}
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define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
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entry:
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; ARM-LABEL: t7:
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; ARM-NOT: lsleq
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; ARM: andeq r2, r2, r2, lsl #1
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; T2-LABEL: t7:
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; T2-NOT: lsleq.w
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; T2: andeq.w r2, r2, r2, lsl #1
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%tmp1 = shl i32 %c, 1
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%cond = icmp eq i32 %a, %b
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%tmp2 = select i1 %cond, i32 %tmp1, i32 -1
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%tmp3 = and i32 %c, %tmp2
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ret i32 %tmp3
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}
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; Fold ORRri into movcc.
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define i32 @t8(i32 %a, i32 %b) nounwind {
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; ARM-LABEL: t8:
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; ARM: cmp r0, r1
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; ARM: orrge r0, r1, #1
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; T2-LABEL: t8:
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; T2: cmp r0, r1
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; T2: orrge r0, r1, #1
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%x = or i32 %b, 1
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %a, i32 %x
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ret i32 %tmp1
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}
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; Fold ANDrr into movcc.
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define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
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; ARM-LABEL: t9:
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; ARM: cmp r0, r1
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; ARM: andge r0, r1, r2
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; T2-LABEL: t9:
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; T2: cmp r0, r1
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; T2: andge.w r0, r1, r2
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%x = and i32 %b, %c
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %a, i32 %x
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ret i32 %tmp1
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}
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; Fold EORrs into movcc.
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define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
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; ARM-LABEL: t10:
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; ARM: cmp r0, r1
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; ARM: eorge r0, r1, r2, lsl #7
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; T2-LABEL: t10:
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; T2: cmp r0, r1
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; T2: eorge.w r0, r1, r2, lsl #7
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%s = shl i32 %c, 7
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%x = xor i32 %b, %s
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %a, i32 %x
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ret i32 %tmp1
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}
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; Fold ORRri into movcc, reversing the condition.
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define i32 @t11(i32 %a, i32 %b) nounwind {
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; ARM-LABEL: t11:
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; ARM: cmp r0, r1
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; ARM: orrlt r0, r1, #1
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; T2-LABEL: t11:
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; T2: cmp r0, r1
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; T2: orrlt r0, r1, #1
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%x = or i32 %b, 1
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %x, i32 %a
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ret i32 %tmp1
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}
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; Fold ADDri12 into movcc
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define i32 @t12(i32 %a, i32 %b) nounwind {
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; ARM-LABEL: t12:
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; ARM: cmp r0, r1
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; ARM: addge r0, r1,
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; T2-LABEL: t12:
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; T2: cmp r0, r1
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; T2: addwge r0, r1, #3000
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%x = add i32 %b, 3000
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%cond = icmp slt i32 %a, %b
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%tmp1 = select i1 %cond, i32 %a, i32 %x
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ret i32 %tmp1
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}
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; Handle frame index operands.
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define void @pr13628() nounwind uwtable align 2 {
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%x3 = alloca i8, i32 256, align 8
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%x4 = load i8, i8* undef, align 1
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%x5 = icmp ne i8 %x4, 0
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%x6 = select i1 %x5, i8* %x3, i8* null
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call void @bar(i8* %x6) nounwind
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ret void
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}
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declare void @bar(i8*)
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; Fold zext i1 into predicated add
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define i32 @t13(i32 %c, i32 %a) nounwind readnone ssp {
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entry:
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; ARM: t13
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; ARM: cmp r1, #10
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; ARM: addgt r0, r0, #1
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; T2: t13
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; T2: cmp r1, #10
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; T2: addgt r0, #1
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%cmp = icmp sgt i32 %a, 10
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%conv = zext i1 %cmp to i32
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%add = add i32 %conv, %c
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ret i32 %add
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}
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; Fold sext i1 into predicated sub
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define i32 @t14(i32 %c, i32 %a) nounwind readnone ssp {
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entry:
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; ARM: t14
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; ARM: cmp r1, #10
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; ARM: subgt r0, r0, #1
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; T2: t14
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; T2: cmp r1, #10
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; T2: subgt r0, #1
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%cmp = icmp sgt i32 %a, 10
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%conv = sext i1 %cmp to i32
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%add = add i32 %conv, %c
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ret i32 %add
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}
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; Do not fold the xor into the select
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define i32 @t15(i32 %p) {
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entry:
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; ARM-LABEL: t15:
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; ARM: mov [[REG:r[0-9]+]], #2
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; ARM: cmp r0, #8
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; ARM: movwgt [[REG:r[0-9]+]], #1
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; ARM: eor r0, [[REG:r[0-9]+]], #1
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; T2-LABEL: t15:
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; T2: movs [[REG:r[0-9]+]], #2
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; T2: cmp [[REG:r[0-9]+]], #8
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; T2: it gt
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; T2: movgt [[REG:r[0-9]+]], #1
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; T2: eor r0, [[REG:r[0-9]+]], #1
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%cmp = icmp sgt i32 %p, 8
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%a = select i1 %cmp, i32 1, i32 2
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%xor = xor i32 %a, 1
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ret i32 %xor
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}
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define i32 @t16(i32 %x, i32 %y) {
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entry:
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; ARM-LABEL: t16:
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; ARM: and r0, {{r[0-9]+}}, {{r[0-9]+}}
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; T2-LABEL: t16:
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; T2: ands r0, {{r[0-9]+}}
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%cmp = icmp eq i32 %x, 0
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%cond = select i1 %cmp, i32 5, i32 2
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%cmp1 = icmp eq i32 %y, 0
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%cond2 = select i1 %cmp1, i32 3, i32 4
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%and = and i32 %cond2, %cond
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ret i32 %and
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}
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define i32 @t17(i32 %x, i32 %y) #0 {
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entry:
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; ARM-LABEL: t17:
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; ARM: and r0, {{r[0-9]+}}, {{r[0-9]+}}
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; T2-LABEL: t17:
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; T2: ands r0, {{r[0-9]+}}
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%cmp = icmp eq i32 %x, -1
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%cond = select i1 %cmp, i32 5, i32 2
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%cmp1 = icmp eq i32 %y, -1
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%cond2 = select i1 %cmp1, i32 3, i32 4
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%and = and i32 %cond2, %cond
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ret i32 %and
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}
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define i32 @t18(i32 %x, i32 %y) #0 {
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entry:
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; ARM-LABEL: t18:
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; ARM: and r0, {{r[0-9]+}}, {{r[0-9]+}}
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; T2-LABEL: t18:
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; T2: and.w r0, {{r[0-9]+}}
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%cmp = icmp ne i32 %x, 0
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%cond = select i1 %cmp, i32 5, i32 2
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%cmp1 = icmp ne i32 %x, -1
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%cond2 = select i1 %cmp1, i32 3, i32 4
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%and = and i32 %cond2, %cond
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ret i32 %and
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}
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define i32 @t19(i32 %x, i32 %y) #0 {
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entry:
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; ARM-LABEL: t19:
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; ARM: orr r0, {{r[0-9]+}}, {{r[0-9]+}}
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; T2-LABEL: t19:
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; T2: orrs r0, {{r[0-9]+}}
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%cmp = icmp ne i32 %x, 0
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%cond = select i1 %cmp, i32 5, i32 2
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%cmp1 = icmp ne i32 %y, 0
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%cond2 = select i1 %cmp1, i32 3, i32 4
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%or = or i32 %cond2, %cond
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ret i32 %or
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}
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define i32 @t20(i32 %x, i32 %y) #0 {
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entry:
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; ARM-LABEL: t20:
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; ARM: orr r0, {{r[0-9]+}}, {{r[0-9]+}}
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; T2-LABEL: t20:
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; T2: orrs r0, {{r[0-9]+}}
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%cmp = icmp ne i32 %x, -1
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%cond = select i1 %cmp, i32 5, i32 2
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%cmp1 = icmp ne i32 %y, -1
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%cond2 = select i1 %cmp1, i32 3, i32 4
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%or = or i32 %cond2, %cond
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ret i32 %or
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}
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define <2 x i32> @t21(<2 x i32> %lhs, <2 x i32> %rhs) {
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; CHECK-LABEL: t21:
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; CHECK-NOT: eor
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; CHECK: mvn
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; CHECK-NOT: eor
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%tst = icmp eq <2 x i32> %lhs, %rhs
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%ntst = xor <2 x i1> %tst, <i1 1 , i1 undef>
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%btst = sext <2 x i1> %ntst to <2 x i32>
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ret <2 x i32> %btst
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}
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