Matthias Braun dd1a6e074d AArch64: Relax assert about large shift sizes. ... The reason why these large shift sizes happen is because OpaqueConstants currently inhibit alot of DAG combining, but that has to be addressed in another commit (like the proposal in D6946). Differential Revision: http://reviews.llvm.org/D6940 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230355 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-24 18:52:04 +00:00
..
AArch64	AArch64: Relax assert about large shift sizes.	2015-02-24 18:52:04 +00:00
ARM	ARM: treat [N x i32] and [N x i64] as AAPCS composite types	2015-02-24 17:22:34 +00:00
BPF	bpf: add missing lit.local.cfg	2015-01-24 18:20:52 +00:00
CPP
Generic	overloaded-intrinsic-name: exercise anyptr on struct	2015-01-27 20:03:08 +00:00
Hexagon	[Hexagon] Factoring classes out of store patterns.	2015-02-09 20:33:46 +00:00
Inputs
Mips	Beginning of alloca implementation for Mips fast-isel	2015-02-24 02:36:45 +00:00
MSP430
NVPTX	[NVPTX] Emit .pragma "nounroll" for loops marked with nounroll	2015-02-01 02:27:45 +00:00
PowerPC	I incorrectly marked the VORC instruction as isCommutable when I added it.	2015-02-20 15:54:58 +00:00
R600	R600/SI: Remove isel mubuf legalization	2015-02-24 17:59:19 +00:00
SPARC	SelectionDAG: fold (fp_to_u/sint (s/uint_to_fp)) here too	2015-02-16 21:47:58 +00:00
SystemZ	[SystemZ] Support all TLS access models - CodeGen part	2015-02-18 09:13:27 +00:00
Thumb
Thumb2	Make buildbots better.	2015-02-11 12:24:09 +00:00
X86	Revert r230280: "Bugfix: SCEVExpander incorrectly marks increment operations as no-wrap"	2015-02-24 16:19:29 +00:00
XCore	Revert r229944: EH: Prune unreachable resume instructions during Dwarf EH preparation	2015-02-20 02:15:36 +00:00