Bill Wendling 47aa9a2bb5 Make sure we add the predicate after all of the registers are added. ...

<rdar://problem/12183003>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162703 91177308-0d34-0410-b5e6-96231b3b80d8

2012-08-27 22:12:44 +00:00

..

ARM

Make sure we add the predicate after all of the registers are added.

2012-08-27 22:12:44 +00:00

CellSPU

Add test triples to fix win32 failures. Revert workaround from r161292.

2012-08-08 20:31:37 +00:00

CPP

test commit

2012-07-18 17:53:05 +00:00

Generic

BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle

2012-08-24 18:14:27 +00:00

Hexagon

Infer instruction properties from single-instruction patterns.

2012-08-24 22:46:53 +00:00

MBlaze

…

Mips

Disable Mips' delay slot filler when optimization level is O0.

2012-08-24 20:40:15 +00:00

MSP430

Reapply r161633-161634 "Partition use lists so defs always come before uses.""

2012-08-10 00:21:30 +00:00

NVPTX

…

PowerPC

Lower constant pools and jump tables via TOC on PPC64/SVR4.

2012-08-24 16:26:02 +00:00

SPARC

test/CodeGen/SPARC/private.ll: Fixup. Forgot to prune old RUN lines.

2012-07-03 04:29:20 +00:00

Thumb

Fix the remaining TCL-style quotes found in the testsuite. This is

2012-07-02 19:09:46 +00:00

Thumb2

Add ADD and SUB to the predicable ARM instructions.

2012-08-16 23:21:55 +00:00

X86

llvm/test/CodeGen/X86/fma.ll: Add -march=x86, or two tests would fail on non-x86 hosts.

2012-08-27 11:50:26 +00:00

XCore

Fix pattern for MKMSK instruction.

2012-06-13 17:59:12 +00:00